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1. 发明授权

US5258631A Semiconductor device having a two-dimensional electron gas as an active layer 失效
标题翻译：具有二维电子气体作为活性层的半导体装置
公开(公告)号：US5258631A
公开(公告)日：1993-11-02
申请号：US884878
申请日：1992-05-18
申请人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
发明人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
IPC分类号： H01L21/18 , H01L21/285 , H01L21/331 , H01L21/335 , H01L27/06 , H01L29/737 , H01L29/778 , H01L29/06 , H01L29/167 , H01L29/30 , H01L31/072
CPC分类号： H01L29/66318 , H01L21/182 , H01L21/28587 , H01L27/0605 , H01L29/66462 , H01L29/7373 , H01L29/7787
摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.
摘要翻译：本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。前者通过应用其源极和漏极区域的形成来制造通过引入杂质例如通过离子注入引起异质结的紊乱的技术或通过形成由选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。这些半导体器件可以降低源极栅极电阻和寄生基极电阻。本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

2. 发明授权

US5381027A Semiconductor device having a heterojunction and a two dimensional gas as an active layer 失效
标题翻译：具有异质结和二维气体作为有源层的半导体器件
公开(公告)号：US5381027A
公开(公告)日：1995-01-10
申请号：US134622
申请日：1993-10-12
申请人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
发明人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
IPC分类号： H01L21/18 , H01L21/285 , H01L21/331 , H01L21/335 , H01L27/06 , H01L29/737 , H01L29/778 , H01L29/804 , H01L29/784
CPC分类号： H01L29/66318 , H01L21/182 , H01L21/28587 , H01L27/0605 , H01L29/66462 , H01L29/7373 , H01L29/7787
摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.
摘要翻译：本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。这些半导体器件可以降低源极栅极电阻和寄生基极电阻。本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

3. 发明授权

US5373191A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5373191A
公开(公告)日：1994-12-13
申请号：US998856
申请日：1992-12-30
申请人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
发明人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
IPC分类号： H01L21/285 , H01L21/331 , H01L21/335 , H01L21/337 , H01L21/338 , H01L21/60 , H01L21/8252 , H01L23/485 , H01L29/812 , H01L29/80 , H01L23/48 , H01L29/06 , H01L29/48
CPC分类号： H01L21/76897 , H01L21/28587 , H01L21/8252 , H01L23/485 , H01L29/66318 , H01L29/66462 , H01L29/66863 , H01L29/66871 , H01L29/66924 , H01L29/8128 , H01L2924/0002
摘要： Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors. Such semiconductor devices can readily be produced by forming a gate electrode metal with a self-alignment process using the lift-off method.
摘要翻译：具有凹陷栅电极金属的场效应晶体管的源电极和漏电极金属通过限定凹部的侧壁的绝缘膜直接连接到面向栅电极金属的高杂质浓度半导体层。源电极和漏电极金属可以通过侧绝缘膜设置成面对栅电极金属。通过这种布置，可以降低场效应晶体管的栅电极和另一电极之间的寄生电阻，以降低半导体层与源电极和漏电极之间的接触电阻，以减小凹陷栅电极的电容并且有利地增加源极栅极击穿电压。上述布置特别适用于采用化合物半导体的晶体管，并且还可以应用于场效应晶体管以外的半导体器件。这种半导体器件可以容易地通过使用剥离法形成具有自对准工艺的栅电极金属来制造。

4. 发明授权

US5181087A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5181087A
公开(公告)日：1993-01-19
申请号：US340471
申请日：1989-04-19
申请人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
发明人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
IPC分类号： H01L21/285 , H01L21/331 , H01L21/335 , H01L21/337 , H01L21/338 , H01L21/60 , H01L21/8252 , H01L23/485 , H01L29/812
CPC分类号： H01L21/76897 , H01L21/28587 , H01L21/8252 , H01L23/485 , H01L29/66318 , H01L29/66462 , H01L29/66863 , H01L29/66871 , H01L29/66924 , H01L29/8128 , H01L2924/0002
摘要： Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors. Such semiconductor devices can readily be produced by forming a gate electrode metal with a self-alignment process using the lift-off method.
摘要翻译：具有凹陷栅电极金属的场效应晶体管的源电极和漏电极金属通过限定凹部的侧壁的绝缘膜直接连接到面向栅电极金属的高杂质浓度半导体层。源电极和漏电极金属可以通过侧绝缘膜设置成面对栅电极金属。通过这种布置，可以降低场效应晶体管的栅电极和另一电极之间的寄生电阻，以降低半导体层与源电极和漏电极之间的接触电阻，以减小凹陷栅电极的电容并且有利地增加源极栅极击穿电压。上述布置特别适用于采用化合物半导体的晶体管，并且还可以应用于场效应晶体管以外的半导体器件。这种半导体器件可以容易地通过使用剥离法形成具有自对准工艺的栅电极金属来制造。

5. 发明申请

US20070257332A1 BIPOLAR TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：US20070257332A1
公开(公告)日：2007-11-08
申请号：US11775716
申请日：2007-07-10
申请人： Atsushi KUROKAWA , Masao Yamane , Yoshinori Imamura
发明人： Atsushi KUROKAWA , Masao Yamane , Yoshinori Imamura
IPC分类号： H01L27/082
CPC分类号： H01L29/7371 , H01L29/1004 , H01L29/66318
摘要： A bipolar transistor having the enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film for masking thereby to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront, and the increase of resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have the enhanced characteristics.
摘要翻译：具有增强特性的双极晶体管通过蚀刻形成在发射极台面（上部发射极层）和基底电极下方的基底台面而制成，以在其大致矩形区域的边缘上具有突起区域。形成掩模膜例如绝缘膜以覆盖矩形区域和突起区域，并且通过使用用于掩蔽的绝缘膜来蚀刻基底层，从而形成基底台面。因此，可以防止沿着基极和发射极台面所面对的区域的边缘上的基极和发射极台面发生异常蚀刻，并且可以防止基极层和发射极层之间的电阻的增加，由此双极晶体管可以具有增强的特性。

6. 发明授权

US07256433B2 Bipolar transistor and a method of manufacturing the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07256433B2
公开(公告)日：2007-08-14
申请号：US10833142
申请日：2004-04-28
申请人： Atsushi Kurokawa , Masao Yamane , Yoshinori Imamura
发明人： Atsushi Kurokawa , Masao Yamane , Yoshinori Imamura
IPC分类号： H01L29/739
CPC分类号： H01L29/7371 , H01L29/1004 , H01L29/66318
摘要： A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have enhanced characteristics.
摘要翻译：具有增强特性的双极晶体管通过蚀刻形成在发射极台面（上部发射极层）和基底电极下方的基底台面而制成，以便在其大致矩形区域的边缘上具有突起区域。形成掩模膜例如绝缘膜以覆盖矩形区域和突起区域，并且通过使用绝缘膜作为掩模蚀刻基底层以形成基底台面。因此，可以防止在基极和发射极台面彼此面对的区域的边缘上的基极和发射极台面发生异常蚀刻，并且可以防止基极层和发射极层之间的电阻的增加。由此双极晶体管可以具有增强的特性。

7. 发明授权

US07411487B2 Tire-information administration system 失效
标题翻译：轮胎信息管理系统
公开(公告)号：US07411487B2
公开(公告)日：2008-08-12
申请号：US10542765
申请日：2004-01-20
申请人： Koji Takao , Tatehiko Yamada , Yoshinori Imamura
发明人： Koji Takao , Tatehiko Yamada , Yoshinori Imamura
IPC分类号： B60C23/02
CPC分类号： B60C23/0416 , B60C23/007 , B60C23/0437 , B60C23/044 , B60C23/0444 , B60C23/045
摘要： A tire-information administration system includes a plurality of sensor modules installed in tires; at least one reception module configured to receive data from the sensor modules; and a central control module configured to command the reception module to acquire data from the sensor modules. The central control module includes a predetermined number of connection ports for the reception module, assigned in advance to each sensor modules; and a specifically configured control means. The control means sequentially outputs at predetermined sampling time a command of data acquisition from a sensor module, to the connection port assigned to each sensor module; assigns the connection port to the sensor module for the next sampling, when there is a data input from the sensor module in response to the command; assigns data acquisition from the sensor module to another connection port, and assigns the other connection port to the sensor module for the next sampling, when there is no data input from the sensor module even by the command issuance. Thus, the tire-information administration system maintains communications even in case of troubles of the reception modules or damages of tires.
摘要翻译：轮胎信息管理系统包括安装在轮胎中的多个传感器模块; 至少一个接收模块，被配置为从所述传感器模块接收数据; 以及中央控制模块，其被配置为命令所述接收模块从所述传感器模块获取数据。中央控制模块包括用于接收模块的预定数量的连接端口，预先分配给每个传感器模块; 和具体配置的控制装置。控制装置在预定的采样时间顺序地将从传感器模块获得数据的命令输出到分配给每个传感器模块的连接端口; 当传感器模块响应命令有数据输入时，将连接端口分配给传感器模块进行下一次采样; 将传感器模块的数据采集分配给另一个连接端口，并且即使通过命令发出也没有传感器模块的数据输入，也可以将其他连接端口分配给传感器模块进行下一个采样。因此，轮胎信息管理系统即使在接收模块的故障或轮胎的损坏的情况下也保持通信。

8. 发明申请

US20060093015A1 Method device and recording medium where program is recorded, for deciding residual travel life and end of life of run-flat tire that continues traveling in run-flat condition 有权
标题翻译：记录程序的方法装置和记录介质，用于确定在平稳状态下继续行驶的漏气轮胎的剩余行程寿命和寿命结束
公开(公告)号：US20060093015A1
公开(公告)日：2006-05-04
申请号：US10524262
申请日：2003-08-12
申请人： Eiji Ichihara , Yoshinori Imamura , Takehiko Yamada
发明人： Eiji Ichihara , Yoshinori Imamura , Takehiko Yamada
IPC分类号： G01K1/08
CPC分类号： B60C23/0408 , B60C23/20 , G01K13/08
摘要： There are provided a process and the like for judging a residual lifetime of a run-flat tire and an end stage of the residual lifetime thereof during continuous running at a run-flat state. The process for judging the residual lifetime of the tire of the invention is characterized in that in a vehicle equipped with a run-flat tire system comprising run-flat tires 2 and detection units 4 each arranged in the respective tire 2 and capable of measuring an atmosphere temperature in at least an interior 3 of the tire 2, when the tire 2 is continuously run at the run-flat state by an extreme lowering of an internal pressure accompanied with the occurrence of puncture or the like, after a limit temperature being statistically an occurrence of trouble is previously set, the atmosphere temperature inside tire of the run-flat tire continuously running at the run-flat state is measured, and a runnable time and/or distance until the run-flat tire results in trouble is predicted by using the atmosphere temperature inside tire measured and data calculated therefrom.
摘要翻译：提供了一种用于在连续运行中的平坦状态下判断漏气保用轮胎的剩余寿命和剩余寿命的终止阶段的过程等。用于判断本发明的轮胎的残余寿命的方法的特征在于，在配备有排气轮胎2和检测单元4的排气轮胎系统的车辆中，每个排气轮胎2和检测单元4分别布置在相应的轮胎2中并且能够测量在轮胎2的至少内部3中的气氛温度，当轮胎2在极限温度为统计学上时，由于伴随着穿刺等的发生的内部压力的极度降低而在平坦状态下连续运行预先设定故障的发生，测量在平坦状态下连续行驶的漏气保用轮胎的轮胎内的气氛温度，直到排气轮胎产生麻烦的运行时间和/或距离由使用测量的轮胎内部的气氛温度和由此计算的数据。

9. 发明申请

US20060057789A1 Method for manufacturing semiconductor device 失效
公开(公告)号：US20060057789A1
公开(公告)日：2006-03-16
申请号：US11266259
申请日：2005-11-04
申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

10. 再颁专利

USRE33094E Electrophotographic member with alpha-si layers 失效
标题翻译：具有α-si层的电子照相元件
公开(公告)号：USRE33094E
公开(公告)日：1989-10-17
申请号：US162312
申请日：1986-09-11
申请人： Eiichi Maruyama , Sachio Ishioka , Yoshinori Imamura , Hirokazu Matsubara , Yasuharu Shimomoto , Shinkichi Horigome , Yoshio Taniguchi
发明人： Eiichi Maruyama , Sachio Ishioka , Yoshinori Imamura , Hirokazu Matsubara , Yasuharu Shimomoto , Shinkichi Horigome , Yoshio Taniguchi
IPC分类号： G03G5/08 , G03G5/082 , H01L21/205 , H01L31/08
CPC分类号： G03G5/08235 , G03G5/08221
摘要： In an electrophotographic member employing an amorphous silicon photoconductive layer, a part which is at least 10 nm thick inwardly of the amorphous silicon layer from the surface (or interface) of the amorphous silicon layer is made of amorphous silicon which has an optical forbidden band gap of at least 1.6 eV and a resistivity of at least 10.sup.10 .OMEGA..cm. The electrophotographic member exhibits a satisfactory resolution and good dark-decay characteristics. Further, a region which has an optical forbidden band gap narrower than that of the amorphous silicon forming the surface (or interface) region is disposed within the amorphous silicon layer to a thickness of at least 10 nm, whereby the sensitivity of the electrophotographic member to longer wavelengths of light can be enhanced.

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