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1. 发明授权

US5208782A Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement 失效
标题翻译：具有多个存储块和片上芯片（LOC）布置的半导体集成电路器件
公开(公告)号：US5208782A
公开(公告)日：1993-05-04
申请号：US892708
申请日：1992-05-29
申请人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
发明人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
IPC分类号： G06F11/18 , G06F11/20 , G11C11/406 , G11C29/00 , H01L27/105 , H01L27/108
CPC分类号： G11C29/808 , G11C11/406 , G11C29/88 , H01L24/06 , H01L27/10805 , G06F11/1666 , G06F11/183 , H01L2224/4826 , H01L27/105 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.
摘要翻译：提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。在芯片上提供了多个宏单元存储块通用的其他外围电路。宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

2. 发明授权

US5426613A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5426613A
公开(公告)日：1995-06-20
申请号：US972907
申请日：1992-11-06
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

3. 发明授权

US5805513A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
公开(公告)号：US5805513A
公开(公告)日：1998-09-08
申请号：US432867
申请日：1995-05-02
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

4. 发明授权

US5217917A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5217917A
公开(公告)日：1993-06-08
申请号：US496280
申请日：1990-03-20
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

5. 发明授权

US5151772A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5151772A
公开(公告)日：1992-09-29
申请号：US616705
申请日：1990-11-20
申请人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
发明人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
IPC分类号： H01L23/522 , H01L27/108
CPC分类号： H01L23/5226 , H01L27/10805 , H01L2924/0002 , Y10S257/923
摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.
摘要翻译：提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。还提供了将外围电路彼此耦合的布线层。该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

6. 发明授权

US5301142A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5301142A
公开(公告)日：1994-04-05
申请号：US895598
申请日：1992-06-08
申请人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
发明人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/34 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/10
摘要： Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.
摘要翻译：在字线和位线延伸的方向上，多个存储器阵列中的每一个被分成多个存储器块MAT00L-MAT07L到MAT10R-MAT17R。提供了与这些存储垫对应并且与字线平行设置的第一公共数据线，即子IO线。指定对应的存储器垫的位线选择性地连接到第一公共数据线。还提供第二公共数据线，即主IO线组MIOG0-MIOG7，并且与位线并行设置。指定的子IO线选择性地连接到第二公共数据线。此外，形成主放大器单元MAU0的多个主放大器在位线延伸的方向上有序排列。这些包括第一主放大器，其包括需要相对大的工作电流的静态电流镜放大器，以及包括仅需要较小工作电流的动态CMOS锁存放大器的第二主放大器。这些主放大器按照所涉及的工作模式正确使用。由于这些布置，动态RAM的多位并行测试模式中的并行比特数可以扩展，而不受对应于每个存储器垫的子IO线数的限制。

7. 发明申请

US20050250609A1 Thin autotensioner 失效
标题翻译：薄自动张力器
公开(公告)号：US20050250609A1
公开(公告)日：2005-11-10
申请号：US11174540
申请日：2005-07-06
申请人： Kazumasa Ayukawa , Hiromi Matsuura
发明人： Kazumasa Ayukawa , Hiromi Matsuura
IPC分类号： F16H7/08 , F16H7/12
CPC分类号： F16H7/1218 , F16H2007/081 , F16H2007/084 , Y10T29/49615
摘要： An autotensioner comprises a torsion coil spring interposed between a base and a rocking arm, and a tubular bushing provided between an inside surface of the base and an outside surface of the rocking arm. The torsion coil spring pushes and biases the rocking arm toward the bushing, and brings the pushing direction substantially in coincidence with the axial load direction of the force, acting on a stepped bolt supporting the rocking arm, from a belt. When the belt tension becomes high, the arm axial center displaces slightly from the base axial center, an extremely large first damping force acts on the rocking arm. When the belt tension becomes low, the smaller second damping force acts on the rocking arm.
摘要翻译：自动张紧器包括设置在基座和摇臂之间的扭力线圈弹簧，以及设置在基座的内表面和摇臂的外表面之间的管状衬套。扭转螺旋弹簧将摇臂朝向衬套推动并偏压，并且使推动方向基本上与作用在支撑摇臂的阶梯螺栓上的力的轴向载荷方向一致。当带张力变高时，臂轴向中心从基座轴心稍微移动，极大的第一阻尼力作用在摇臂上。当皮带张力变低时，较小的第二阻尼力作用在摇臂上。

8. 发明授权

US5669843A Actuator 失效
标题翻译：执行器
公开(公告)号：US5669843A
公开(公告)日：1997-09-23
申请号：US629499
申请日：1996-04-10
申请人： Brian Lewis Bolton , Yoshio Yuyama , Katsutoshi Akutagawa , Hiromi Matsuura
发明人： Brian Lewis Bolton , Yoshio Yuyama , Katsutoshi Akutagawa , Hiromi Matsuura
IPC分类号： E05B53/00 , E05B65/12 , F16H19/00 , F16H35/00
CPC分类号： E05B81/25 , F16H19/00 , E05B53/008
摘要： An actuator comprises a housing member including a motor compartment and a gear compartment, the gear compartment having inner teeth formed on the inner periphery thereof, a motor having a rotary shaft with a motor gear mounted thereon, the motor being housed in the motor compartment in such a way as to permit the motor gear to project into the gear compartment, an output shaft projecting outwardly from the housing member, a larger diameter gear housed in the gear compartment which is rotatable about the output shaft and held in mesh engagement with the motor gear, a smaller diameter gear disposed coaxially with the larger diameter gear and rotatable in conjunction with the rotation of the larger diameter gear, a planet gear held in mesh engagement with both the smaller diameter gear and the inner teeth formed in the gear compartment so that the planet gear can shift its engagement position with respect to the inner teeth as the smaller diameter gear rotates, and a rotary member engaging the planet gear for rotation within the gear compartment, the output shaft being rotatable in response to the rotation of the rotary member.
摘要翻译：致动器包括包括马达室和齿轮室的壳体构件，齿轮室具有形成在其内周上的内齿，马达具有安装在其上的马达齿轮的旋转轴，马达容纳在马达室中这种方式使得马达齿轮能够突出到齿轮室中，从壳体构件向外突出的输出轴，容纳在齿轮室中的较大直径的齿轮，其可围绕输出轴转动并与马达保持啮合齿轮，与较大直径齿轮同轴设置并与大直径齿轮的旋转一起旋转的较小直径的齿轮，与形成在齿轮室中的较小直径齿轮和内齿啮合的行星齿轮，使得当小直径齿轮旋转时，行星齿轮可以相对于内齿移动其接合位置，并且旋转构件接合使行星齿轮在齿轮室内旋转，输出轴可响应旋转构件的旋转而旋转。

9. 发明授权

US4849939A Semiconductor memorizing device 失效
标题翻译：半导体记忆装置
公开(公告)号：US4849939A
公开(公告)日：1989-07-18
申请号：US100752
申请日：1987-09-24
申请人： Masaya Muranaka , Hiromi Matsuura , Kanehide Kenmizaki , Osamu Okayama
发明人： Masaya Muranaka , Hiromi Matsuura , Kanehide Kenmizaki , Osamu Okayama
IPC分类号： G11C11/401 , G11C8/00 , G11C29/00 , G11C29/04 , G11C29/42
CPC分类号： G11C29/835 , G11C8/00
摘要： A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.
摘要翻译：具有连接到存储单元的存储器阵列，第一和第二选择线的半导体存储器以及选择选择线之一的选择装置。选择装置包括选择电路，当与第一选择线对应的地址信号与预定的地址信号对准时，可选地选择第一选择线或第二选择线。

10. 发明授权

US07384355B2 Thin autotensioner 失效
标题翻译：薄自动张力器
公开(公告)号：US07384355B2
公开(公告)日：2008-06-10
申请号：US11174540
申请日：2005-07-06
申请人： Kazumasa Ayukawa , Hiromi Matsuura
发明人： Kazumasa Ayukawa , Hiromi Matsuura
IPC分类号： F16H7/08 , F16H7/18
CPC分类号： F16H7/1218 , F16H2007/081 , F16H2007/084 , Y10T29/49615
摘要： An autotensioner comprises a torsion coil spring interposed between a base and a rocking arm, and a tubular bushing provided between an inside surface of the base and an outside surface of the rocking arm. The torsion coil spring pushes and biases the rocking arm toward the bushing, and brings the pushing direction substantially in coincidence with the axial load direction of the force, acting on a stepped bolt supporting the rocking arm, from a belt. When the belt tension becomes high, the arm axial center displaces slightly from the base axial center, an extremely large first damping force acts on the rocking arm. When the belt tension becomes low, the smaller second damping force acts on the rocking arm.
摘要翻译：自动张紧器包括设置在基座和摇臂之间的扭力线圈弹簧，以及设置在基座的内表面和摇臂的外表面之间的管状衬套。扭转螺旋弹簧将摇臂朝向衬套推动并偏压，并且使推动方向基本上与作用在支撑摇臂的阶梯螺栓上的力的轴向载荷方向一致。当带张力变高时，臂轴向中心从基座轴心稍微移动，极大的第一阻尼力作用在摇臂上。当皮带张力变低时，较小的第二阻尼力作用在摇臂上。

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