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1. 发明授权

US5208782A Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement 失效
标题翻译：具有多个存储块和片上芯片（LOC）布置的半导体集成电路器件
公开(公告)号：US5208782A
公开(公告)日：1993-05-04
申请号：US892708
申请日：1992-05-29
申请人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
发明人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
IPC分类号： G06F11/18 , G06F11/20 , G11C11/406 , G11C29/00 , H01L27/105 , H01L27/108
CPC分类号： G11C29/808 , G11C11/406 , G11C29/88 , H01L24/06 , H01L27/10805 , G06F11/1666 , G06F11/183 , H01L2224/4826 , H01L27/105 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.
摘要翻译：提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。在芯片上提供了多个宏单元存储块通用的其他外围电路。宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

2. 发明授权

US5264712A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5264712A
公开(公告)日：1993-11-23
申请号：US881314
申请日：1992-05-07
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L21/308 , H01L29/66
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

3. 发明授权

US5734188A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
公开(公告)号：US5734188A
公开(公告)日：1998-03-31
申请号：US674185
申请日：1996-07-01
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L27/105 , H01L29/76 , H01L29/94 , H01L31/062 , H01L3/119
CPC分类号： H01L27/105
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

4. 发明授权

US5917211A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5917211A
公开(公告)日：1999-06-29
申请号：US979543
申请日：1997-11-25
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/08 , H01L29/76 , H01L29/94
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

5. 发明授权

US07941241B2 Optical fabrication method 有权
标题翻译：光学制造方法
公开(公告)号：US07941241B2
公开(公告)日：2011-05-10
申请号：US11751847
申请日：2007-05-22
申请人： Norio Takinami , Toshio Maeda
发明人： Norio Takinami , Toshio Maeda
IPC分类号： G06F19/00 , A61F2/28
CPC分类号： G02B1/12 , B33Y80/00 , Y10S623/901
摘要： An optical fabrication method which is capable of adjusting a hardness and a density needed for each optical fabrication area in fabricating a three-dimensional fabricated article through sintering with a light beam, and is excellent in a working efficiency performs the steps of forming a powder layer of a predetermined thickness and then sintering the powder layer with a light beam, a predetermined number of times, cutting a periphery of the powder layers, and changing a degree of sintering by changing an amount of irradiation per unit area of a light-beam sintered surface according to a shortest distance from a peripheral surface of each powder layer.
摘要翻译：一种光学制造方法，其能够通过用光束烧结来调整制造三维制品的每个光学制造区域所需的硬度和密度，并且工作效率优异地执行以下步骤：形成粉末层预定厚度，然后用光束烧结粉末层，预定次数，切割粉末层的周边，并且通过改变光束烧结单位面积的照射量来改变烧结程度根据与每个粉末层的外周表面的最短距离的表面。

6. 发明授权

US5948803A N-substituted dioxothiazolidylbenzamide derivatives and process for producing the same 失效
标题翻译： N-取代的二氧代噻唑烷基苯甲酰胺衍生物及其制备方法
公开(公告)号：US5948803A
公开(公告)日：1999-09-07
申请号：US77899
申请日：1998-06-16
申请人： Toshio Maeda , Masahiro Nomura , Katsuya Awano , Susumu Kinoshita , Hiroya Satoh , Koji Murakami , Masaki Tsunoda
发明人： Toshio Maeda , Masahiro Nomura , Katsuya Awano , Susumu Kinoshita , Hiroya Satoh , Koji Murakami , Masaki Tsunoda
IPC分类号： C07D277/20 , A61K31/425 , A61K31/426 , A61K31/44 , A61P3/06 , A61P3/08 , A61P43/00 , C07D277/34 , C07D417/12
CPC分类号： C07D417/12 , C07D277/34
摘要： The invention provides novel N-substituted dioxothiazolidylbenzamide derivatives that improve the insulin resistance and have potent hypoglycemic effect and lipid-lowering effect, and the process for preparing them, and relates to N-substituted dioxothiazolidylbenzamide derivatives characterized by being represented by a general formula (1) ##STR1## �wherein R.sup.1 and R.sup.2 denote identically or differently hydrogen atoms, lower alkyl groups with carbon atoms of 1 to 4, lower alkoxy groups with carbon atoms of 1 to 3, lower haloalkyl groups with carbon atoms of 1 to 3, lower haloalkoxy groups with carbon atoms of 1 to 3, halogen atoms or hydroxyl groups, or R.sup.1 and R.sup.2 combine to form a methylenedioxy group, R.sup.3 denotes a hydrogen atom, lower alkoxys group with carbon atoms of 1 to 3, hydroxyl group or halogen atom, R.sup.4 denotes a hydrogen or lower alkyl group with carbon atoms of 1 to 3, n denotes an integer of 0 to 2, and X denotes N or CH!, and process for preparing the same.
摘要翻译： PCT No.PCT / JP96 / 03664 Sec。 371日期：1998年6月16日 102（e）日期1998年6月16日PCT 1996年12月16日PCT公布。公开号WO97 / 22600 PCT 日期：1997年6月26日本发明提供了改善胰岛素抵抗并具有强效降血糖作用和降脂作用的新型N-取代二氧代噻唑烷基苯甲酰胺衍生物及其制备方法，涉及N-取代二氧代噻唑烷基苯甲酰胺衍生物，其特征在于以通式（1）[其中R 1和R 2表示相同或不同的氢原子，碳原子数1〜4的低级烷基，碳原子数1〜3的低级烷氧基，碳原子数1〜3的低级卤代烷基碳原子数为1〜3的低级卤代烷氧基，卤素原子或羟基或R1和R2结合形成亚甲二氧基，R3表示氢原子，碳原子数1〜3的低级烷氧基，羟基或卤素原子，R4表示碳原子数为1〜3的氢原子或低级烷基，n表示0〜2的整数，X表示N或CH]表示的化合物及其制备方法。

7. 发明授权

US5449787A N,N'-disubstituted amide derivatives 失效
标题翻译： N，N'-二取代酰胺衍生物
公开(公告)号：US5449787A
公开(公告)日：1995-09-12
申请号：US290785
申请日：1994-09-06
申请人： Mitsutomo Miyashita , Toshio Maeda , Fumio Kawahara , Fukutaro Taga
发明人： Mitsutomo Miyashita , Toshio Maeda , Fumio Kawahara , Fukutaro Taga
IPC分类号： A61K31/40 , A61K31/404 , A61K31/416 , A61P1/00 , A61P1/08 , A61P25/04 , A61P25/06 , A61P25/18 , C07D401/06 , C07D403/06 , A61K31/415 , C07D209/12 , C07D231/56
CPC分类号： C07D401/06 , C07D403/06
摘要： N,N'-disubstituted amide derivatives having potent and selective antagonistic action to 5-HT.sub.3 receptor have been developed by the present invention, which provides antagonistic drugs to 5-HT.sub.3 receptor containing novel N,N'-disubstituted amide derivatives represented by a general formula [I] ##STR1## (wherein R.sub.1 denotes a hydrogen atom or lower alkyl group, R.sub.2 and R.sub.3, which may be identical or different, denote respectively a hydrogen atom, lower alkyl group, lower alkenyl group, nonsubstituted or substituted aryl-lower alkyl group, acyl group or lower alkoxycarbonyl group, R.sub.4 denotes a hydrogen atom, lower alkyl group or lower alkoxy group, A denotes CH or N, and n denotes 1), their hydrates or acid addition salts.
摘要翻译： PCT No.PCT / JP93 / 00269 Sec。 371日期：1994年9月6日 102（e）1994年9月6日PCT PCT 1993年3月3日PCT公布。出版物WO93 / 18025 日本9月16日，N，已经通过本发明开发了对5-HT 3受体具有有效和选择性拮抗作用的N'-二取代酰胺衍生物，其提供拮抗药物至5-HT 3受体的新型N，由通式[I]或低级烷基表示的二取代酰胺衍生物，可以相同或不同的R 2和R 3分别表示氢原子，低级烷基，低级烯基，未取代或取代的芳基 - 低级烷基，酰基或低级烷氧基羰基，R4表示氢原子，低级烷基或低级烷氧基，A表示CH或N，n表示1），它们的水合物或酸加成盐。

8. 发明授权

US08944706B2 Printer, printing system and printing method 有权
标题翻译：打印机，打印系统和打印方式
公开(公告)号：US08944706B2
公开(公告)日：2015-02-03
申请号：US12730599
申请日：2010-03-24
申请人： Takashi Sakamoto , Toshio Maeda , Hiroshi Tomiya
发明人： Takashi Sakamoto , Toshio Maeda , Hiroshi Tomiya
IPC分类号： B41J3/60 , B41J11/46
CPC分类号： B41J3/60 , B41J11/46
摘要： The first image which is a continuous image divided into pages is printed on the first surface of web by the first printer, and the start mark is printed at the head of each page. The second image which is a continuous image is printed on the second surface by the second printer in synchronization with recording synchronization pulses. In printing of the second image, obtained is a difference between the number of pulses inputted to the second printing mechanism between detections of preceding and succeeding start marks, and the number of pulses estimated to be inputted thereto in the case where expansion or shrinkage of web doesn't occur, to adjust the frequency of pulses on the basis of the difference. Therefore, the second image is printed in accordance with the first image on the web without being affected by expansion or shrinkage of web.
摘要翻译：作为分割成页的连续图像的第一图像由第一打印机印刷在纸幅的第一表面上，并且在每页的头部印刷起始标记。作为连续图像的第二图像与记录同步脉冲同步地由第二打印机印刷在第二表面上。在第二图像的打印中，获得的是在前后开始标记的检测之间输入到第二打印机构的脉冲数与估计输入的脉冲数之间的差异，在幅材的膨胀或收缩的情况下不发生，根据差异来调整脉冲的频率。因此，第二图像根据幅材上的第一图像而被印刷而不受幅材的膨胀或收缩的影响。

9. 发明授权

US06980189B2 Liquid crystal display 有权
标题翻译：液晶显示器
公开(公告)号：US06980189B2
公开(公告)日：2005-12-27
申请号：US10141942
申请日：2002-05-10
申请人： Yoshio Maruoka , Toshiki Misonou , Toshio Maeda , Akihiro Watanabe , Hideki Nakagawa
发明人： Yoshio Maruoka , Toshiki Misonou , Toshio Maeda , Akihiro Watanabe , Hideki Nakagawa
IPC分类号： G02F1/133 , G09G3/00 , G09G3/20 , G09G3/36 , G09G5/00 , H04N5/74
CPC分类号： G09G3/2011 , G09G3/001 , G09G3/20 , G09G3/2092 , G09G3/3614 , G09G3/3648 , G09G3/3655 , G09G5/005 , G09G5/006 , G09G2300/0876 , G09G2310/0232 , G09G2320/0209 , G09G2320/0233 , G09G2320/0247 , G09G2320/0276 , G09G2320/0285 , G09G2320/0606 , G09G2320/0613 , G09G2320/0626 , G09G2320/066 , G09G2320/0673 , G09G2320/0693 , G09G2330/12 , G09G2340/0435 , G09G2352/00
摘要： In a liquid crystal display device which inputs analogue video signals after phase development, the deterioration of display quality due to the irregularities of circuit can be reduced. To correct the irregularities due to a plurality of analogue circuits, the liquid crystal display device includes look up tables for a plurality of analogue circuits in the inside of a digital signal processing circuit. The liquid crystal display device performs the correction of irregularities of the analogue circuits based on data set in the look up tables.
摘要翻译：在相位显影后输入模拟视频信号的液晶显示装置中，由于电路的不规则性，显示质量的恶化可以降低。为了校正由于多个模拟电路引起的不规则性，液晶显示装置包括数字信号处理电路内部的多个模拟电路的查找表。液晶显示装置根据查找表中设定的数据进行模拟电路的不规则的校正。

10. 发明授权

US5129507A Roller conveyor 失效
标题翻译：滚筒输送机
公开(公告)号：US5129507A
公开(公告)日：1992-07-14
申请号：US665843
申请日：1991-03-07
申请人： Toshio Maeda , Yoshihiko Fujio
发明人： Toshio Maeda , Yoshihiko Fujio
IPC分类号： B65G47/26
CPC分类号： B65G47/261
摘要： A roller conveyor in which articles are supported by idler rollers carried by a main frame and conveyed as the idler rollers are driven into rotation. A plurality of first idler rollers are arranged in one of two side frames of the main frame. A plurality of second idler rollers capable of supporting articles in pair with the first idler rollers are arranged in the other side frame. Driving force for conveying articles is given to the first idler rollers only. The fact that first idler rollers and second idler rollers are separately arranged at opposite sides assures that the first and second idler rollers are of short and light construction.

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