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1. 发明授权

US5301142A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5301142A
公开(公告)日：1994-04-05
申请号：US895598
申请日：1992-06-08
申请人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
发明人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/34 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/10
摘要： Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.
摘要翻译：在字线和位线延伸的方向上，多个存储器阵列中的每一个被分成多个存储器块MAT00L-MAT07L到MAT10R-MAT17R。提供了与这些存储垫对应并且与字线平行设置的第一公共数据线，即子IO线。指定对应的存储器垫的位线选择性地连接到第一公共数据线。还提供第二公共数据线，即主IO线组MIOG0-MIOG7，并且与位线并行设置。指定的子IO线选择性地连接到第二公共数据线。此外，形成主放大器单元MAU0的多个主放大器在位线延伸的方向上有序排列。这些包括第一主放大器，其包括需要相对大的工作电流的静态电流镜放大器，以及包括仅需要较小工作电流的动态CMOS锁存放大器的第二主放大器。这些主放大器按照所涉及的工作模式正确使用。由于这些布置，动态RAM的多位并行测试模式中的并行比特数可以扩展，而不受对应于每个存储器垫的子IO线数的限制。

2. 发明授权

US5208782A Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement 失效
标题翻译：具有多个存储块和片上芯片（LOC）布置的半导体集成电路器件
公开(公告)号：US5208782A
公开(公告)日：1993-05-04
申请号：US892708
申请日：1992-05-29
申请人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
发明人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
IPC分类号： G06F11/18 , G06F11/20 , G11C11/406 , G11C29/00 , H01L27/105 , H01L27/108
CPC分类号： G11C29/808 , G11C11/406 , G11C29/88 , H01L24/06 , H01L27/10805 , G06F11/1666 , G06F11/183 , H01L2224/4826 , H01L27/105 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.
摘要翻译：提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。在芯片上提供了多个宏单元存储块通用的其他外围电路。宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

3. 发明授权

US5514905A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5514905A
公开(公告)日：1996-05-07
申请号：US329824
申请日：1994-10-27
申请人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
发明人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
IPC分类号： H01L23/29 , H01L23/495 , H01L23/48 , H01L29/41
CPC分类号： H01L23/4951 , H01L23/293 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48599 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14
摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.
摘要翻译：半导体器件与半导体芯片相连，该半导体芯片在与其前表面或第一主表面的中心位置相对应的部分处具有多个接合焊盘;半导体芯片，覆盖在半导体芯片上并具有开口与接合焊盘相对应，多个有机绝缘膜上的引线以及密封或封装这些成分的成型树脂。

4. 再颁专利

USRE37539E1 Sealed stacked arrangement of semiconductor devices 有权
标题翻译：密封堆叠布置的半导体器件
公开(公告)号：USRE37539E1
公开(公告)日：2002-02-05
申请号：US09471000
申请日：1999-12-23
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： H01L2328
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2225/1029 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。堆叠这样连接的DRAM芯片和引线框架的多对，引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

5. 发明授权

US5594279A Semiconductor device having shield wiring for noise suppression 失效
标题翻译：具有用于噪声抑制的屏蔽布线的半导体器件
公开(公告)号：US5594279A
公开(公告)日：1997-01-14
申请号：US149876
申请日：1993-11-10
申请人： Yutaka Itou , Hidetoshi Iwai , Toshiyuki Sakuta , Takumi Nasu , Tomohiro Suzuki
发明人： Yutaka Itou , Hidetoshi Iwai , Toshiyuki Sakuta , Takumi Nasu , Tomohiro Suzuki
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/522 , H01L23/552 , H01L23/48
CPC分类号： H01L24/06 , H01L23/5225 , H01L23/552 , H01L24/05 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/06136 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/4826 , H01L2224/48464 , H01L2224/49113 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025
摘要： A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8. Since the coupling impedance between shield wiring 1 and substrate 7 (due almost solely to the electrostatic capacitance Css) is large, and coupling impedance between Vss wiring 2 and substrate 7 (due almost solely to the junction capacitance D) is low, the noise caused by variations in the potential of substrate 7 is transferred to shield wiring 1, while it is not appreciably transferred to Vss wiring 2.
摘要翻译：一种半导体器件，其中屏蔽布线布置在半导体衬底和用于提供电源电位或接地电位的电源布线之间。基本上防止了由半导体衬底的电位变化所表示的噪声通过屏蔽布线转移到上述电源布线。在一个方面，屏蔽布线1布置在用于向半导体衬底和衬底7上的各种电路供电的Vss布线之间。该屏蔽布线1经由M1片内布线4，M2片内连接到接地引线框架18 布线5，连接部40，接合焊盘3和接合线8.由于屏蔽布线1和基板7之间的耦合阻抗（几乎完全相当于静电电容Css），所以Vss布线2和基板7 由于几乎完全由结电容D）导致的，基板7的电位的变化引起的噪声被传送到屏蔽布线1，而不明显地转移到Vss布线2。

6. 发明授权

US5410507A Special mode control method for dynamic random access memory 失效
标题翻译：动态随机存取存储器的特殊模式控制方法
公开(公告)号：US5410507A
公开(公告)日：1995-04-25
申请号：US977212
申请日：1992-11-16
申请人： Masanori Tazunoki , Shigetoshi Sakomura , Toshitsugu Takekuma , Yutaka Ito , Kazuya Ito , Wataru Arakawa , Hidetoshi Iwai , Toshiyuki Sakuta , Masamichi Ishihara
发明人： Masanori Tazunoki , Shigetoshi Sakomura , Toshitsugu Takekuma , Yutaka Ito , Kazuya Ito , Wataru Arakawa , Hidetoshi Iwai , Toshiyuki Sakuta , Masamichi Ishihara
IPC分类号： G11C11/4074 , G11C11/4076 , G11C13/00
CPC分类号： G11C11/4076 , G11C11/4074
摘要： A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.
摘要翻译：提供了具有旨在低功耗的数据保留模式的动态RAM。在数据保持模式下，产生电压降低，电压升高，参考电压等的电压产生电路的电流供应能力在保持存储器单元的信息保持操作的范围内被限制，并且所选择的数量相对于在正常读/写模式和刷新模式中选择的存储器垫，数据保持模式中的存储器垫增加。通过组合地址选通信号和其他控制信号来设置数据保持模式等特殊模式，执行虚拟CBR刷新以释放特殊模式。

7. 发明授权

US5309011A Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein 失效
标题翻译：晶圆规模或全晶圆存储器系统，其封装方法和其中采用的晶片处理方法
公开(公告)号：US5309011A
公开(公告)日：1994-05-03
申请号：US960848
申请日：1992-10-14
申请人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
发明人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
IPC分类号： H01L23/14 , H01L23/32 , H01L23/538 , H01L25/065 , H01L25/07 , H01L27/02 , H01L27/10 , H01L27/15
CPC分类号： H01L23/147 , H01L23/32 , H01L23/5385 , H01L25/0652 , H01L25/073 , H01L2224/0401 , H01L2224/16225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48464 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152 , H01L2924/3025
摘要： To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
摘要翻译：为了实现全尺寸晶片存储器或晶片级积分存储器系统的更高的封装密度和一个晶片级，晶片以预定的间隔彼此垂直堆叠。改进了封装技术，使得可以精确地实现存储器系统布局并且可以形成精确的通孔。此外，其他芯片固定在晶片上，从而进一步实现高封装密度。

8. 发明申请

US20050051898A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050051898A1
公开(公告)日：2005-03-10
申请号：US10970027
申请日：2004-10-22
申请人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
发明人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/485 , H01L23/52 , H01L23/528 , H01L27/04 , H01L23/48
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10162 , H01L2924/1306 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.
摘要翻译：在由铝构成的最上层布线层和由铜构成的正下方的布线层的半导体装置中，最上层的布线层比其正下方的布线层厚，因此最上层布线层的薄层电阻比接线层正下方。多个环形电源线VR和焊盘PD由最上面的布线层形成，并且环形电源线VR和焊盘PD分别通过最上面布线层的电力线VLB1连接。因此，可以减小从焊盘PD到环形电源线VR的馈电路径上的电压降，并且可以稳定从焊盘PD到环形电源线VR的电力传导。

9. 发明授权

US5818743A Low power multiplier 失效
标题翻译：低功率乘法器
公开(公告)号：US5818743A
公开(公告)日：1998-10-06
申请号：US426349
申请日：1995-04-21
申请人： Wai Lee , Toshiyuki Sakuta
发明人： Wai Lee , Toshiyuki Sakuta
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F2207/3884
摘要： A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.
摘要翻译：数字乘法器110，用于乘以表示被乘数的多个被乘数信号X0-X23和表示乘法器的多个乘法器信号Y0-Y23。在其中，从乘法器信号和乘法器信号产生多个中间结果信号，例如部分乘积信号。还提供了多个加法器电路40，用于将中间结果信号相加以产生表示乘法和乘法器相乘的结果的多个最终结果信号，其中至少一些加法器电路接收表示中间加法结果的第一信号，至少两个先前的加法器级并且还接收表示作为仅一次加法的结果产生的中间结果的第二信号。最后，将多个延迟元件70放置在所选择的第二信号线中，以便将第二信号的到达延迟到至少一些加法器电路，以便将输入的到达同步到至少一些加法器电路。

10. 发明授权

US5701031A Sealed stacked arrangement of semiconductor devices 失效
标题翻译：密封堆叠布置的半导体器件
公开(公告)号：US5701031A
公开(公告)日：1997-12-23
申请号：US280381
申请日：1994-07-25
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L23/28 , H01L23/535 , H01L23/538
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。堆叠这样连接的DRAM芯片和引线框架的多对，并且引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

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