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1. 发明申请

US20070066009A1 SIDEWALL IMAGE TRANSFER (SIT) TECHNOLOGIES 失效
标题翻译： SIDEWALL图像传输（SIT）技术
公开(公告)号：US20070066009A1
公开(公告)日：2007-03-22
申请号：US11162662
申请日：2005-09-19
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Kirk Peterson
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Kirk Peterson
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132
摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.
摘要翻译：一种结构制造方法。该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。然后，定位区域缩进。然后，在结构的暴露于环境的表面上形成保形层。然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。然后，去除封盖区域，以将定位区域暴露于周围环境。然后，移除定位区域，以将存储区域暴露于周围环境。然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

2. 发明申请

US20070166848A1 METHOD AND STRUCTURE TO PREVENT CIRCUIT NETWORK CHARGING DURING FABRICATION OF INTEGRATED CIRCUITS 失效
标题翻译：在整合电路制造过程中防止电路网络充电的方法和结构
公开(公告)号：US20070166848A1
公开(公告)日：2007-07-19
申请号：US11687711
申请日：2007-03-19
申请人： Jeffrey Gambino , Kirk Peterson
发明人： Jeffrey Gambino , Kirk Peterson
IPC分类号： H01L21/00 , H01L21/82
CPC分类号： H01L27/1203 , H01L23/5256 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.
摘要翻译：集成电路及其制造方法。该集成电路包括：一个或多个配电网络; 一个或多个地面分配网络; 一个或多个数据网络; 并且将相同或不同网络的电力，地线或数据线临时并电连接在一起，从由一个或多个配电网络，一个或多个配电网络，一个或多个配电网络组成的组中选择的相同或不同的网络，更多数据网络及其组合。

3. 发明申请

US20060286778A1 METHOD OF MANUFACTURING DUAL ORIENTATION WAFERS 失效
标题翻译：制造双取向波的方法
公开(公告)号：US20060286778A1
公开(公告)日：2006-12-21
申请号：US11160365
申请日：2005-06-21
申请人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
发明人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译：公开了制造双取向晶片的方法。在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。另外的隔离结构形成在沟槽内和半导体层内的硅材料内。对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

4. 发明申请

US20060273397A1 PROTECT DIODES FOR HYBRID-ORIENTATION SUBSTRATE STRUCTURES 失效
标题翻译：用于混合基底结构的保护二极管
公开(公告)号：US20060273397A1
公开(公告)日：2006-12-07
申请号：US10908926
申请日：2005-06-01
申请人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
发明人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括具有不同晶格取向的第一和第二硅区的混合取向嵌段。第一硅区域直接在块上，而第二硅区域通过电介质区域与块物理隔离。第一和第二晶体管分别形成在第一和第二区域上。此外，在第一掺杂放电预防结构防止对第一晶体管的放电损坏的块上形成第一和第二掺杂放电预防结构，而第二掺杂放电预防结构在等离子体处理期间防止对第二晶体管的放电损坏。在第一和第二晶体管的正常操作期间，第一和第二放电预防结构表现得像电介质区域。

5. 发明授权

US08253399B2 Reconfigurable regulator and associated method 有权
标题翻译：可重构调节器及相关方法
公开(公告)号：US08253399B2
公开(公告)日：2012-08-28
申请号：US12273055
申请日：2008-11-18
申请人： Kirk Peterson , Qunying Li
发明人： Kirk Peterson , Qunying Li
IPC分类号： G05F1/56 , G05F1/565 , G05F1/569 , G05F1/575
CPC分类号： H02M3/1588 , H02M2001/0045 , Y02B70/1466
摘要： One embodiment of the invention includes a regulator system that includes a high-side power transistor electrically connected between a first node and a second node. The system also includes a low-side power transistor electrically connected between the second node and a third node. The high and low-side power transistors can be controlled by high and low-side control signals, respectively. A mode controller provides at least one mode control signal having a value to enable operation of the regulator system in each of a buck switching, boost switching, negative switching, and linear regulator mode. The regulator system can utilize at least one of the high-side power transistor and the low-side power transistor to operate in the selected mode depending on at least one of an input voltage and an arrangement of external circuitry that are electrically coupled to at least one of the first, second, and third nodes to provide a regulated output voltage.
摘要翻译：本发明的一个实施例包括调节器系统，其包括电连接在第一节点和第二节点之间的高侧功率晶体管。该系统还包括电连接在第二节点和第三节点之间的低侧功率晶体管。高低侧功率晶体管可分别由高低侧控制信号控制。模式控制器提供至少一个具有值的模式控制信号，以便在降压切换，升压切换，负切换和线性调节器模式中的每一个中实现调节器系统的操作。调节器系统可以利用高边功率晶体管和低侧功率晶体管中的至少一个以所选择的模式工作，这取决于至少一个输入电压和外部电路的布置中的至少一个，其至少电耦合到第一，第二和第三节点之一，以提供稳定的输出电压。

6. 发明申请

US20070287275A1 METHOD FOR FABRICATING DOPED POLYSILICON LINES 审中-公开
标题翻译：用于制造掺杂多晶硅线的方法
公开(公告)号：US20070287275A1
公开(公告)日：2007-12-13
申请号：US11835745
申请日：2007-08-08
申请人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
发明人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
IPC分类号： H01L21/425
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：在衬底的顶表面上形成电介质层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，N掺杂物质基本上包含在多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

7. 发明申请

US20080096370A1 METHOD OF MANUFACTURING DUAL ORIENTATION WAFERS 有权
标题翻译：制造双取向波的方法
公开(公告)号：US20080096370A1
公开(公告)日：2008-04-24
申请号：US11955436
申请日：2007-12-13
申请人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
发明人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译：公开了制造双取向晶片的方法。在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。另外的隔离结构形成在沟槽内和半导体层内的硅材料内。对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

8. 发明申请

US20070293025A1 PROTECT DIODES FOR HYBRID-ORIENTATION SUBSTRATE STRUCTURES 失效
标题翻译：用于混合基底结构的保护二极管
公开(公告)号：US20070293025A1
公开(公告)日：2007-12-20
申请号：US11849489
申请日：2007-09-04
申请人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
发明人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.
摘要翻译：半导体结构制造方法。首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向。接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

9. 发明申请

US20060267137A1 METHOD AND STRUCTURE TO PREVENT CIRCUIT NETWORK CHARGING DURING FABRICATION OF INTEGRATED CIRCUITS 失效
标题翻译：在整合电路制造过程中防止电路网络充电的方法和结构
公开(公告)号：US20060267137A1
公开(公告)日：2006-11-30
申请号：US10908720
申请日：2005-05-24
申请人： Jeffrey Gambino , Kirk Peterson
发明人： Jeffrey Gambino , Kirk Peterson
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L23/5256 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.
摘要翻译：集成电路及其制造方法。该集成电路包括：一个或多个配电网络; 一个或多个地面分配网络; 一个或多个数据网络; 并且将相同或不同网络的电力，地线或数据线临时并电连接在一起，从由一个或多个配电网络，一个或多个配电网络，一个或多个配电网络组成的组中选择的相同或不同的网络，更多数据网络及其组合。

10. 发明申请

US20060163670A1 DUAL SILICIDE PROCESS TO IMPROVE DEVICE PERFORMANCE 审中-公开
标题翻译：双硅工艺提高器件性能
公开(公告)号：US20060163670A1
公开(公告)日：2006-07-27
申请号：US10905945
申请日：2005-01-27
申请人： John Ellis-Monaghan , Dale Martin , William Murphy , James Nakos , Kirk Peterson
发明人： John Ellis-Monaghan , Dale Martin , William Murphy , James Nakos , Kirk Peterson
IPC分类号： H01L29/76
CPC分类号： H01L29/7845 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/4933 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region and an n-type device region; a first-type suicide contact to the n-type device region; the first-type suicide having a work function that is substantially aligned to the n-type device region conduction band; and a second-type silicide contact to the p-type device region; the second-type silicide having a work function that is substantially aligned to the p-type device region valence band. The present invention also provides a semiconducting structure and a method of forming therefore, in which the silicide contact material and silicide contact processing conditions are selected to provide strain based device improvements in pFET and nFET devices.
摘要翻译：半导体结构及其形成方法包括具有p型器件区域和n型器件区域的衬底; 与n型器件区域的第一类型的硅化物接触; 具有基本上与n型器件区域导带对准的功函数的第一型硅化物; 和与p型器件区域的第二类型硅化物接触; 所述第二类型硅化物具有基本上对准所述p型器件区域价带的功函数。本发明还提供了半导体结构及其形成方法，其中选择硅化物接触材料和硅化物接触处理条件以在pFET和nFET器件中提供基于应变的器件改进。

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