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1. 发明申请

US20060073689A1 METHOD FOR FABRICATING DOPED POLYSILICON LINES 有权
标题翻译：用于制造掺杂多晶硅线的方法
公开(公告)号：US20060073689A1
公开(公告)日：2006-04-06
申请号：US10711771
申请日：2004-10-04
申请人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
发明人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
IPC分类号： H01L21/3205
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

2. 发明申请

US20070287275A1 METHOD FOR FABRICATING DOPED POLYSILICON LINES 审中-公开
标题翻译：用于制造掺杂多晶硅线的方法
公开(公告)号：US20070287275A1
公开(公告)日：2007-12-13
申请号：US11835745
申请日：2007-08-08
申请人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
发明人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
IPC分类号： H01L21/425
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：在衬底的顶表面上形成电介质层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，N掺杂物质基本上包含在多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

3. 发明申请

US20060163670A1 DUAL SILICIDE PROCESS TO IMPROVE DEVICE PERFORMANCE 审中-公开
标题翻译：双硅工艺提高器件性能
公开(公告)号：US20060163670A1
公开(公告)日：2006-07-27
申请号：US10905945
申请日：2005-01-27
申请人： John Ellis-Monaghan , Dale Martin , William Murphy , James Nakos , Kirk Peterson
发明人： John Ellis-Monaghan , Dale Martin , William Murphy , James Nakos , Kirk Peterson
IPC分类号： H01L29/76
CPC分类号： H01L29/7845 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/4933 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region and an n-type device region; a first-type suicide contact to the n-type device region; the first-type suicide having a work function that is substantially aligned to the n-type device region conduction band; and a second-type silicide contact to the p-type device region; the second-type silicide having a work function that is substantially aligned to the p-type device region valence band. The present invention also provides a semiconducting structure and a method of forming therefore, in which the silicide contact material and silicide contact processing conditions are selected to provide strain based device improvements in pFET and nFET devices.
摘要翻译：半导体结构及其形成方法包括具有p型器件区域和n型器件区域的衬底; 与n型器件区域的第一类型的硅化物接触; 具有基本上与n型器件区域导带对准的功函数的第一型硅化物; 和与p型器件区域的第二类型硅化物接触; 所述第二类型硅化物具有基本上对准所述p型器件区域价带的功函数。本发明还提供了半导体结构及其形成方法，其中选择硅化物接触材料和硅化物接触处理条件以在pFET和nFET器件中提供基于应变的器件改进。

4. 发明申请

US20070296006A1 STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元的结构
公开(公告)号：US20070296006A1
公开(公告)日：2007-12-27
申请号：US11850776
申请日：2007-09-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

5. 发明申请

US20070145438A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20070145438A1
公开(公告)日：2007-06-28
申请号：US11681454
申请日：2007-03-02
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

6. 发明申请

US20060286778A1 METHOD OF MANUFACTURING DUAL ORIENTATION WAFERS 失效
标题翻译：制造双取向波的方法
公开(公告)号：US20060286778A1
公开(公告)日：2006-12-21
申请号：US11160365
申请日：2005-06-21
申请人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
发明人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译：公开了制造双取向晶片的方法。在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。另外的隔离结构形成在沟槽内和半导体层内的硅材料内。对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

7. 发明申请

US20080096370A1 METHOD OF MANUFACTURING DUAL ORIENTATION WAFERS 有权
标题翻译：制造双取向波的方法
公开(公告)号：US20080096370A1
公开(公告)日：2008-04-24
申请号：US11955436
申请日：2007-12-13
申请人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
发明人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译：公开了制造双取向晶片的方法。在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。另外的隔离结构形成在沟槽内和半导体层内的硅材料内。对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

8. 发明申请

US20070187734A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 失效
标题翻译：具有增强电容的CMOS成像器光电二极管
公开(公告)号：US20070187734A1
公开(公告)日：2007-08-16
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于形成在基底表面处的掺杂层的下方。

9. 发明申请

US20060226456A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20060226456A1
公开(公告)日：2006-10-12
申请号：US10907570
申请日：2005-04-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

10. 发明申请

US20060102939A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 审中-公开
公开(公告)号：US20060102939A1
公开(公告)日：2006-05-18
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

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