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1. 发明申请

US20090277895A1 MOUNTING TABLE STRUCTURE, AND PROCESSING APPARATUS 有权
标题翻译：安装台结构和加工设备
公开(公告)号：US20090277895A1
公开(公告)日：2009-11-12
申请号：US12505282
申请日：2009-07-17
申请人： Tomohito KOMATSU , Hirohiko Yamamoto , Daisuke Toriya
发明人： Tomohito KOMATSU , Hirohiko Yamamoto , Daisuke Toriya
IPC分类号： F27D11/00 , A47B37/00
CPC分类号： H01L21/67103 , C23C16/4586
摘要： A mounting table body made of ceramic includes power-receiving conductor portions and buried therein. A surface of mounting table body is formed with a recessed connection hole and a connection terminal electrically jointed to the power-receiving conductor portion and exposed into the connection hole, the connection terminal being made of a high-melting-point metal, an alloy thereof or a compound thereof. A power-feeding line member provided with a power-feeding connector portion is inserted at its leading end portion into the connection hole to feed electricity to the power-receiving conductor portion. A stress relaxing member is interposed between the connection terminal and the power-feeding connector portion. The stress relaxing member and the connection terminal are jointed together by a brazing material. The stress relaxing member is made of a metal free from cobalt and nickel or an alloy thereof.
摘要翻译：由陶瓷制成的安装台体包括受电导体部分并埋入其中。安装台体的表面形成有凹入的连接孔和电连接到受电导体部分并暴露于连接孔中的连接端子，连接端子由高熔点金属制成，其合金或其化合物。设置有供电连接器部分的馈电线构件在其前端部插入到连接孔中以将电力馈送到电力接收导体部分。在连接端子和供电连接器部分之间设置应力缓和部件。应力缓和构件和连接端子通过钎焊材料接合在一起。应力松弛部件由不含钴，镍或其合金的金属制成。

2. 发明授权

US08334481B2 Mounting table structure, and processing apparatus 有权
标题翻译：安装台结构和加工设备
公开(公告)号：US08334481B2
公开(公告)日：2012-12-18
申请号：US12505282
申请日：2009-07-17
申请人： Tomohito Komatsu , Hirohiko Yamamoto , Daisuke Toriya
发明人： Tomohito Komatsu , Hirohiko Yamamoto , Daisuke Toriya
IPC分类号： F27B5/14 , F27D11/02 , H05B3/03 , H05B3/08
CPC分类号： H01L21/67103 , C23C16/4586
摘要： A mounting table body made of ceramic includes power-receiving conductor portions and buried therein. A surface of mounting table body is formed with a recessed connection hole and a connection terminal electrically jointed to the power-receiving conductor portion and exposed into the connection hole, the connection terminal being made of a high-melting-point metal, an alloy thereof or a compound thereof. A power-feeding line member provided with a power-feeding connector portion is inserted at its leading end portion into the connection hole to feed electricity to the power-receiving conductor portion. A stress relaxing member is interposed between the connection terminal and the power-feeding connector portion. The stress relaxing member and the connection terminal are jointed together by a brazing material. The stress relaxing member is made of a metal free from cobalt and nickel or an alloy thereof.
摘要翻译：由陶瓷制成的安装台体包括受电导体部分并埋入其中。安装台体的表面形成有凹入的连接孔和电连接到受电导体部分并暴露于连接孔中的连接端子，连接端子由高熔点金属制成，其合金或其化合物。设置有供电连接器部分的馈电线构件在其前端部插入到连接孔中，以将电力馈送到电力接收导体部分。在连接端子和供电连接器部分之间设置应力缓和部件。应力缓和构件和连接端子通过钎焊材料接合在一起。应力松弛部件由不含钴，镍或其合金的金属制成。

3. 发明申请

US20100323313A1 STAGE STRUCTURE AND HEAT TREATMENT APPARATUS 审中-公开
标题翻译：阶段结构和热处理设备
公开(公告)号：US20100323313A1
公开(公告)日：2010-12-23
申请号：US12918244
申请日：2009-03-13
申请人： Daisuke Toriya , Hirohiko Yamamoto
发明人： Daisuke Toriya , Hirohiko Yamamoto
IPC分类号： F27B5/16 , B23Q3/00
CPC分类号： H01L21/68792 , C23C16/4586 , H01L21/67103 , H01L21/67115
摘要： There is provided a stage structure which can prevent the formation of a cool spot in the central portion of a stage, thereby preventing breakage of the stage, and can enhance the in-plane uniformity of heat treatment of a processing object.The stage structure, provided in a treatment container of a heat treatment apparatus, for placing thereon a semiconductor wafer W as a processing object to be heat treated, includes: a stage 52 for placing the processing object on it; and a cylindrical support post 54 jointed to the center of the lower surface of the stage and supporting the stage. A heat reflecting section 56 is provided at an upper position within the support post and close to the lower surface of the stage. The use of the heat reflecting section 56 prevents the formation of a cool spot in the central portion of the stage 54.
摘要翻译：提供了可以防止在台的中心部分形成冷点的台架结构，从而防止工作台的断裂，并且可以增强加工对象的热处理的面内均匀性。设置在热处理装置的处理容器中的用于放置作为待处理的加工对象的半导体晶片W的载物台结构包括：用于将加工对象放置在其上的台52; 以及圆柱形支撑柱54，其连接到台的下表面的中心并且支撑台。热反射部分56设置在支撑柱内的上部位置并靠近平台的下表面。使用热反射部分56防止在台54的中心部分形成冷点。

4. 发明申请

US20120126360A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME 有权
标题翻译：半导体器件及其制造方法及其设计方法
公开(公告)号：US20120126360A1
公开(公告)日：2012-05-24
申请号：US13362385
申请日：2012-01-31
申请人： Kenichi KURODA , Kozo Watanabe , Hirohiko Yamamoto
发明人： Kenichi KURODA , Kozo Watanabe , Hirohiko Yamamoto
IPC分类号： H01L29/06
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/74 , H01L21/76224 , H01L21/76229 , H01L23/522 , H01L23/528 , H01L23/53228 , H01L27/0207 , H01L27/11807 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/4925 , H01L2924/0002 , H01L2924/00
摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
摘要翻译：提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案，在虚拟区域FA中。由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

5. 发明申请

US20110207288A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME 有权
标题翻译：半导体器件及其制造方法及其设计方法
公开(公告)号：US20110207288A1
公开(公告)日：2011-08-25
申请号：US13096246
申请日：2011-04-28
申请人： Kenichi KURODA , Kozo Watanabe , Hirohiko Yamamoto
发明人： Kenichi KURODA , Kozo Watanabe , Hirohiko Yamamoto
IPC分类号： H01L21/302
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/74 , H01L21/76224 , H01L21/76229 , H01L23/522 , H01L23/528 , H01L23/53228 , H01L27/0207 , H01L27/11807 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/4925 , H01L2924/0002 , H01L2924/00
摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
摘要翻译：提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案，在虚拟区域FA中。由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

6. 发明授权

US06717202B2 HSG semiconductor capacitor with migration inhibition layer 失效
标题翻译： HSG半导体电容器具有迁移抑制层
公开(公告)号：US06717202B2
公开(公告)日：2004-04-06
申请号：US10271798
申请日：2002-10-17
申请人： Yasuhiro Sugawara , Ryouichi Furukawa , Toshio Uemura , Akira Takamatsu , Hirohiko Yamamoto , Tadanori Yoshida , Masayuki Ishizaka , Shinpei Iljima , Yuzuru Ohji
发明人： Yasuhiro Sugawara , Ryouichi Furukawa , Toshio Uemura , Akira Takamatsu , Hirohiko Yamamoto , Tadanori Yoshida , Masayuki Ishizaka , Shinpei Iljima , Yuzuru Ohji
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10814 , H01L27/10894 , H01L28/90
摘要： A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
摘要翻译：第一硅膜形成为沿着形成在氧化硅膜50中的沟槽52的内表面延伸，在第一硅膜的表面上形成氧化物膜，并且还沉积第二非晶硅膜。对第二非晶硅膜的表面施加热处理以接种硅核并促进晶粒生长，并且从第二非晶硅膜生长粒状硅晶体57。以这种方式，可以降低电容器件的下电极59的电阻。

7. 发明授权

US06337399B1 Processes for producing 7-isoindolinequinolonecarboxylic derivatives and intermediates therefor, salts of 7-isoindolinequinolonecarboxylic acids, hydrates thereof, and composition containing the same as active ingredient 有权
公开(公告)号：US06337399B1
公开(公告)日：2002-01-08
申请号：US09529407
申请日：2000-04-26
申请人： Minoru Yamada , Shoichi Hamamoto , Kazuya Hayashi , Kazuko Takaoka , Hiroko Matsukura , Minako Yotsuji , Kenji Yonezawa , Katsuji Ojima , Tamotsu Takamatsu , Kyoko Taya , Hirohiko Yamamoto , Taro Kiyoto , Hironori Kotsubo
发明人： Minoru Yamada , Shoichi Hamamoto , Kazuya Hayashi , Kazuko Takaoka , Hiroko Matsukura , Minako Yotsuji , Kenji Yonezawa , Katsuji Ojima , Tamotsu Takamatsu , Kyoko Taya , Hirohiko Yamamoto , Taro Kiyoto , Hironori Kotsubo
IPC分类号： C07D21516
CPC分类号： C07D401/04 , A61K31/4709 , C07C217/48 , C07D209/44 , C07D215/56 , C07F5/025 , Y02P20/55
摘要： This invention relates to processes for producing a 7-isoindoline-quinolonecarboxylic acid derivative represented by the general formula [1] which is useful as an antibacterial agent, and an intermediate thereof: wherein R1 represents a hydrogen atom or a carboxyl-protecting group; R2 represents a substituted or unsubstituted alkyl, alkenyl, cycloalkyl, aryl or heterocyclic group; R3 represents at least one group selected from hydrogen atom, halogen atoms, substituted or unsubstituted alkyl, alkenyl, cycloalkyl, aryl, alkoxy or alkylthio groups, nitro group, cyano group, acyl groups, protected or unprotected hydroxyl groups and protected or unprotected or substituted or unsubstituted amino groups; R4 represents at least one group selected from hydrogen atom, halogen atoms, substituted or unsubstituted alkyl, alkenyl, cycloalkyl, aralkyl, aryl, alkoxy or alkylthio groups, protected or unprotected hydroxyl or imino groups, protected or unprotected or substituted or unsubstituted amino groups, alkylidene groups, oxo group and groups each forming a cycloalkane group together with the carbon atom to which R4 bonds; R5 represents a hydrogen atom, an amino-protecting group, a substituted or unsubstituted alkyl, cycloalkyl, alkylsulfonyl, arylsulfonyl, acyl or aryl group; R6 represents a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl, alkoxy or alkylthio group, a protected or unprotected hydroxyl or amino group or a nitro group; and A represents CH or C—R7 in which R7 represents a halogen atom, a substituted or unsubstituted alkyl, alkoxy or alkylthio group or a protected or unprotected hydroxyl group, and to a salt of a 7-isoindoline-quinolonecarboxylic acid represented by the general formula [1], a hydrate thereof and a composition comprising them as an active ingredient.

8. 发明授权

US5021790A Microwave date transmission apparatus 失效
标题翻译：微波日期传输装置
公开(公告)号：US5021790A
公开(公告)日：1991-06-04
申请号：US522581
申请日：1990-05-14
申请人： Tomozo Ohta , Hiroshi Nakano , Kazutada Higashi , Hirohiko Yamamoto
发明人： Tomozo Ohta , Hiroshi Nakano , Kazutada Higashi , Hirohiko Yamamoto
IPC分类号： G01S13/76 , G01S13/78 , G01S13/82 , G06K7/00 , G06K19/07 , G07C3/00 , G07C9/00
CPC分类号： G01S13/765 , G01S13/78 , G01S13/825 , G06K19/0723 , G06K7/0008 , G07C3/00 , G07C9/00111
摘要： A microwave data transmission apparatus adapted to transmit and receive information by microwaves, in which an identification tag is made smaller in size and lighter in weight to considerably improve the convenience in a setting operation for use in many applications. The apparatus can be applied for production control within a factory or can be used to recognize whether a person wearing an identification tag has entered or left a room.

9. 发明授权

US08426969B2 Semiconductor device having active region and dummy wirings 有权
标题翻译：具有有源区和虚拟布线的半导体器件
公开(公告)号：US08426969B2
公开(公告)日：2013-04-23
申请号：US13362385
申请日：2012-01-31
申请人： Kenichi Kuroda , Kozo Watanabe , Hirohiko Yamamoto
发明人： Kenichi Kuroda , Kozo Watanabe , Hirohiko Yamamoto
IPC分类号： H01L23/48
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/74 , H01L21/76224 , H01L21/76229 , H01L23/522 , H01L23/528 , H01L23/53228 , H01L27/0207 , H01L27/11807 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/4925 , H01L2924/0002 , H01L2924/00
摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
摘要翻译：提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案，在虚拟区域FA中。由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

10. 发明申请

US20060202282A1 Semiconductor device and a method of manufacturing the same and designing the same 有权
标题翻译：半导体装置及其制造方法及其设计方法
公开(公告)号：US20060202282A1
公开(公告)日：2006-09-14
申请号：US11430983
申请日：2006-05-10
申请人： Kenichi Kuroda , Kozo Watanabe , Hirohiko Yamamoto
发明人： Kenichi Kuroda , Kozo Watanabe , Hirohiko Yamamoto
IPC分类号： H01L31/00 , H01L29/94 , H01L29/00 , H01L29/76
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/74 , H01L21/76224 , H01L21/76229 , H01L23/522 , H01L23/528 , H01L23/53228 , H01L27/0207 , H01L27/11807 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/4925 , H01L2924/0002 , H01L2924/00
摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
摘要翻译：提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。根据该技术，可以通过放置相对较宽区域的第一虚拟图案DP 1，将虚拟图案放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的区域，并且在虚拟区域FA中具有相对较小面积的第二虚拟图案DP 2 2 。由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。此外，当虚拟区域FA中的第一伪图案DP 1占据相对较宽的区域时，可以控制掩模数据的增加。

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