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1. 发明授权

US06881597B2 Method of manufacturing a semiconductor device to provide a plurality of test element groups (TEGs) in a scribe region 失效
标题翻译：制造半导体器件以在划线区域中提供多个测试元件组（TEG）的方法
公开(公告)号：US06881597B2
公开(公告)日：2005-04-19
申请号：US10051056
申请日：2002-01-22
申请人： Kyoichiro Asayama , Yasuhiro Mitsui , Fumiko Arakawa , Shiro Kamohara , Yuzuru Ohji
发明人： Kyoichiro Asayama , Yasuhiro Mitsui , Fumiko Arakawa , Shiro Kamohara , Yuzuru Ohji
IPC分类号： G01R31/28 , H01L21/28 , H01L21/3205 , H01L21/66 , H01L21/822 , H01L23/52 , H01L23/544 , H01L27/04 , H01L21/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 μm or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 μm to 0.8 μm to the first electrode pad.
摘要翻译：公开了一种能够通过测量布置在划线区域中的多个TEG来提高半导体器件的产量的技术。连接到TEG的每个端子的第一电极焊盘形成为具有约0.5μm或更短的侧边长度并由半导体衬底上的最上层布线构成的矩形，微小隔离图案，因此，大量 TEG可以放在第一个划痕区域。特征评估或故障分析是通过将具有0.05μm至0.8μm的尖端曲率半径的纳米探针接触到第一电极焊盘来进行的。

2. 发明授权

US06781172B2 Semiconductor device with adhesion-improvement capacitor and process for producing the device 失效
标题翻译：具有粘附改善电容器的半导体器件及其制造方法
公开(公告)号：US06781172B2
公开(公告)日：2004-08-24
申请号：US09800493
申请日：2001-03-08
申请人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
发明人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
IPC分类号： H01L2976
CPC分类号： H01L28/60 , H01L27/10814 , H01L28/55
摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
摘要翻译：一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

3. 发明授权

US06720603B2 CAPACITOR STRUCTURE AND A SEMICONDUCTOR DEVICE WITH A FIRST METAL LAYER, A SECOND METAL SILICIDE LAYER FORMED OVER THE FIRST METAL LAYER AND A SECOND METAL LAYER FORMED OVER THE SECOND METAL SILICIDE LAYER 有权
标题翻译：电容器结构和具有第一金属层的第二金属层的第一金属层和在第二金属硅化物层上形成的第二金属层的第二金属层的半导体器件
公开(公告)号：US06720603B2
公开(公告)日：2004-04-13
申请号：US10321614
申请日：2002-12-18
申请人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
发明人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
IPC分类号： H01L27108
CPC分类号： H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L21/02356 , H01L21/31637 , H01L27/10814 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
摘要翻译：形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

4. 发明授权

US5499207A Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same 失效
标题翻译：具有改善的电极隔离的半导体存储器件及其制造方法
公开(公告)号：US5499207A
公开(公告)日：1996-03-12
申请号：US281568
申请日：1994-07-28
申请人： Hiroshi Miki , Yuzuru Ohji , Shinichi Tachi
发明人： Hiroshi Miki , Yuzuru Ohji , Shinichi Tachi
IPC分类号： H01L21/02 , H01L27/108 , G11C11/24
CPC分类号： H01L28/55 , H01L27/10817 , H01L28/60 , Y10S438/974
摘要： With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.
摘要翻译：随着半导体存储器的尺寸近来的减小，在大容量半导体存储器件的电容器制造过程中通常会出现隔离问题。为了克服这一点，即使这些元件非常靠近在一起，也提供了用于改善电容器元件之间的隔离的布置。例如，如果使用诸如铂的材料作为电容器底部电极，则可以在形成铂之前沉积氧化钛薄层，以提供氧化钛在沟槽的底部上的结构。然后通过化学气相沉积在该结构上形成高介电常数绝缘体。高介电常数绝缘体具有满足铂的化学计量组成并且具有比沟槽底部的化学计量组成更多的钛原子的组成。形成在沟槽底部上的非化学计量组合物层具有低介电常数和高绝缘性，以保持邻接的底部电容器电极之间的电绝缘。此外，由于低结晶，形成具有平坦化形态的层。

5. 发明授权

US4907046A Semiconductor device with multilayer silicon oxide silicon nitride dielectric 失效
标题翻译：具有多层氧化硅氮化硅电介质的半导体器件
公开(公告)号：US4907046A
公开(公告)日：1990-03-06
申请号：US168490
申请日：1988-03-15
申请人： Yuzuru Ohji , Osamu Kasahara , Yoshitaka Tadaki , Hiroko Kaneko , Toshiyuki Mine , Kunihiro Yagi
发明人： Yuzuru Ohji , Osamu Kasahara , Yoshitaka Tadaki , Hiroko Kaneko , Toshiyuki Mine , Kunihiro Yagi
IPC分类号： H01L27/04 , F02B3/06 , H01L21/318 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/51 , H01L29/92 , H01L29/78 , H01L27/02 , H01L29/34
CPC分类号： H01L28/40 , H01L27/10808 , F02B3/06 , H01L29/51
摘要： A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).
摘要翻译：固态器件包括晶体管（A）和电容器（B）。电容器由下多晶硅层或电极（20），多个电介质层（22）和上多晶硅层或电极（30）限定。电介质层通过在下多晶层上气相沉积3.6-18.6nm厚的氮化硅层形成。较厚的氮化硅层增加故障率并降低电容（图8）。更具体地，氮化硅层沉积在多晶硅层的薄的约1nm的氧化膜或表面（24）上。氧化氮化硅层形成二氧化硅层（28），直到氮化硅层仅为约3nm厚。这在氧化层上形成，厚度为1-8.4nm。如果氮化硅层减小到3nm以下，则多晶硅容易迅速氧化，降低电容并增加故障（图8）。

6. 发明申请

US20050024811A1 Semiconductor device with adhesion-improvement capacitor and process for producing the device 失效
标题翻译：具有粘附改善电容器的半导体器件及其制造方法
公开(公告)号：US20050024811A1
公开(公告)日：2005-02-03
申请号：US10923002
申请日：2004-08-23
申请人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
发明人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108 , H01G4/008
CPC分类号： H01L28/60 , H01L27/10814 , H01L28/55
摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
摘要翻译：一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

7. 发明授权

US06583463B1 Semiconductor integrated circuit device with information storage capacitor having ruthenium dioxide lower electrode and crystallized TA2O5 capacitor insulator 失效
标题翻译：具有信息存储电容器的半导体集成电路器件具有二氧化钌下电极和结晶化的TA2O5电容绝缘体
公开(公告)号：US06583463B1
公开(公告)日：2003-06-24
申请号：US09172196
申请日：1998-10-14
申请人： Naruhiko Nakanishi , Nobuyoshi Kobayashi , Yuzuru Ohji , Sinpei Iijima , Yasuhiro Sugawara , Misuzu Kanai
发明人： Naruhiko Nakanishi , Nobuyoshi Kobayashi , Yuzuru Ohji , Sinpei Iijima , Yasuhiro Sugawara , Misuzu Kanai
IPC分类号： H01L27108
CPC分类号： H01L21/31604 , H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L27/10894 , H01L28/56 , H01L28/60 , H01L28/65
摘要： A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.
摘要翻译：一种半导体集成电路器件，包括存储单元，该存储单元包括形成在半导体衬底1的主表面上的存储单元选择MISFET Qs和与所述存储单元选择MISFET Qs串联连接的信息存储电容器C，电极54，电容器绝缘体58和上电极59，其中下电极54由含有二氧化钌（RuO 2）作为主要成分的导电材料制成，并且电容器绝缘体58由结晶的五氧化二钽制成。因此，可以确保256Mbits DRAM的存储单元或后一代的DRAM的存储单元所需的电容。

8. 发明授权

US06451665B1 Method of manufacturing a semiconductor integrated circuit 失效
标题翻译：制造半导体集成电路的方法
公开(公告)号：US06451665B1
公开(公告)日：2002-09-17
申请号：US09459343
申请日：1999-12-13
申请人： Takashi Yunogami , Kazuo Nojiri , Yuzuru Ohji , Sukeyoshi Tsunekawa , Masahiko Hiratani , Yuichi Matsui
发明人： Takashi Yunogami , Kazuo Nojiri , Yuzuru Ohji , Sukeyoshi Tsunekawa , Masahiko Hiratani , Yuichi Matsui
IPC分类号： H01L2120
CPC分类号： H01L27/105 , H01L21/32139 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L28/60
摘要： Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.
摘要翻译：描述了在图案化钌等上使用诸如铂或BST之类的薄膜作为硬掩模的集成电路的制造方法，从而可以在不去除硬掩模的情况下形成器件。另外，本发明的方法可以插入诸如铂的保护膜，以便在去除用于图案化硬掩模的抗蚀剂时，下面的钌膜等被损坏。

9. 发明授权

US5343353A Semiconductor device and process of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5343353A
公开(公告)日：1994-08-30
申请号：US929918
申请日：1992-08-17
申请人： Hiroshi Miki , Yuzuru Ohji , Shinichi Tachi , Keiichi Kanehori
发明人： Hiroshi Miki , Yuzuru Ohji , Shinichi Tachi , Keiichi Kanehori
IPC分类号： H01L27/10 , C23C16/40 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01G4/10 , B05D5/12 , H01G7/00
CPC分类号： H01L28/56 , C23C16/409 , H01L21/31691 , Y10T29/435
摘要： A microminiature, large capacitor for a semiconductor memory is formed from a raw material compound of plural different kinds of metal atoms for deposition, irrespective of the material, temperature and surface condition of a substrate, thereby forming a thin dielectric film having uniform characteristics not affected by the interface even though the film is made as thin as approximately 0.1 .mu.m. The microminiature large capacitance capacitor has a capacitance unaffected by an oxide existing at the interface between a ferroelectric and electrodes without using precious metals such as platinum having the least degree of freedom in deposition of thin films and microminiature processing. The ferroelectric thin film is deposited using an organic metal comprising a plurality of kinds of metal elements in conformity with the composition of a desired dielectric. As electrodes for use in forming a capacitor, a substance exhibiting conductivity after oxidation is preferably employed.
摘要翻译：用于半导体存储器的微型大电容器由用于沉积的多种不同种类的金属原子的原料化合物形成，与基板的材料，温度和表面状况无关，从而形成具有不受影响的均匀特性的薄电介质膜通过界面即使薄膜制成薄约0.1μm。微型大容量电容器具有不受在铁电体和电极之间的界面处存在的氧化物的影响，而不使用贵金属如铂，其沉积薄膜和微型加工具有最小的自由度。使用包含多种金属元素的有机金属，使其与所需电介质的组成一致地沉积铁电薄膜。作为用于形成电容器的电极，优选使用氧化后显示导电性的物质。

10. 发明授权

US4563900A Acoustic microscope 失效
标题翻译：声学显微镜
公开(公告)号：US4563900A
公开(公告)日：1986-01-14
申请号：US603937
申请日：1984-04-26
申请人： Kunio Harada , Sumio Yamaguchi , Hiroshi Kanda , Isao Ishikawa , Yuzuru Ohji
发明人： Kunio Harada , Sumio Yamaguchi , Hiroshi Kanda , Isao Ishikawa , Yuzuru Ohji
IPC分类号： G01N29/28 , G01H3/12 , G01N29/06 , G10K11/02 , G01N29/04
CPC分类号： G10K11/02 , G01H3/125
摘要： In an acoustic microscope wherein an acoustic wave is projected to a predetermined specimen by an acoustic lens, and a disturbed acoustic wave from the specimen is imaged; an acoustic microscope characterized in that the lens has a ring which is arranged around it, whereby a liquid to serve as an acoustic propagation medium is held between the ring and the specimen by capillarity.
摘要翻译：在声波显微镜中，声波通过声透镜投射到预定的样本，并且来自样本的干扰的声波被成像; 一种声学显微镜，其特征在于，透镜具有围绕其布置的环，由此通过毛细作用将用作声传播介质的液体保持在环和样品之间。

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