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1. 发明授权

US4733374A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US4733374A
公开(公告)日：1988-03-22
申请号：US844626
申请日：1986-03-27
申请人： Tohru Furuyama , Shigeyoshi Watanabe , Tatsuo Ikawa
发明人： Tohru Furuyama , Shigeyoshi Watanabe , Tatsuo Ikawa
IPC分类号： H01L27/108 , G11C8/14 , G11C11/408 , G11C11/4097 , G11C7/00
CPC分类号： G11C8/14 , G11C11/408 , G11C11/4097
摘要： A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.
摘要翻译：半导体存储器件具有N个读出放大器，每个读出放大器具有第一和第二输入端，N个第一存储单元，N个第二存储器单元，N个第一位线，每个第一位线连接到同一列的第一存储器单元并连接到第一输入端一个读出放大器的一个端子，以及N个第二位线，每个第二位线连接到同一列的第二存储器单元并连接到一个读出放大器的第二输入端。第一存储器单元形成在第一存储单元区域中，并且第二存储器单元形成在与第一存储单元区域相邻布置的第二存储器单元区域中，并且与第一存储器单元区域相对于读出放大器。

2. 发明授权

US06232822B1 Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism 失效
标题翻译：半导体器件包括被偏置以通过冲击电离机制产生负的基极电流的双极晶体管
公开(公告)号：US06232822B1
公开(公告)日：2001-05-15
申请号：US08268728
申请日：1994-06-30
申请人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
发明人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： H03K17687
CPC分类号： H01L27/1025 , G11C11/39 , H01L29/36 , H01L29/42304 , H01L29/456 , H01L29/73 , H01L29/7322 , H01L29/885 , H03F3/04 , H03K3/021 , H03K17/567
摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE
摘要翻译：半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

3. 发明授权

US5625602A NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines 失效
标题翻译： NAND型动态RAM具有耦合到多开位线的临时存储寄存器和读出放大器
公开(公告)号：US5625602A
公开(公告)日：1997-04-29
申请号：US446291
申请日：1995-05-22
申请人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
发明人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
IPC分类号： G11C7/10 , G11C11/404 , G11C11/4096 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/106 , G11C11/4045 , G11C11/4096 , G11C11/4097 , G11C7/1051 , G11C7/1078
摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.
摘要翻译：读出放大器连接在存储单元阵列之间，重写寄存器布置在与读出放大器相邻的位置，传输门设置在读出放大器和存储单元阵列之间，传输门提供在存储单元的位线之间阵列和全局位线，以及用于控制传输门的栅极控制电路。当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

4. 发明授权

US5467303A Semiconductor memory device having register groups for writing and reading data 失效
标题翻译：具有用于写入和读取数据的寄存器组的半导体存储器件
公开(公告)号：US5467303A
公开(公告)日：1995-11-14
申请号：US380443
申请日：1995-01-30
申请人： Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
发明人： Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
IPC分类号： G11C11/405 , G11C11/401 , G11C11/404 , G11C11/4096 , G11C11/24 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/404
摘要： A semiconductor memory device comprises an array of memory cell units, each of which has a plurality of MOS transistors connected in series and a plurality of information storage capacitors corresponding in number to the MOS transistors and each having its one end connected to the source of a corresponding one of the MOS transistors, and a plurality of register groups each of which is adapted to temporarily store information stored in one of the memory cell units for each column of the array in order to read from and write into each memory cell unit.
摘要翻译：半导体存储器件包括一组存储单元单元，每个存储单元单元具有串联连接的多个MOS晶体管和多个与MOS晶体管相对应的多个信息存储电容器，每个信号存储电容器的一端连接到对应的一个MOS晶体管，以及多个寄存器组，每个寄存器组适于临时存储存储在阵列的每列的存储单元单元之一中的信息，以便从每个存储单元单元读取和写入。

5. 发明授权

US5194762A MOS-type charging circuit 失效
标题翻译： MOS型充电电路
公开(公告)号：US5194762A
公开(公告)日：1993-03-16
申请号：US498622
申请日：1990-03-26
申请人： Takahiko Hara , Syuso Fujii , Shigeyoshi Watanabe
发明人： Takahiko Hara , Syuso Fujii , Shigeyoshi Watanabe
IPC分类号： G11C11/407 , G05F1/56 , G11C5/14 , G11C11/409 , G11C11/413 , H01L21/822 , H01L27/04 , H01M10/44 , H03K19/00 , H03K19/096
CPC分类号： G11C5/147
摘要： In a MOS-type charging circuit in a semiconductor chip using a supply voltage-lowering circuit, a driver MOS transistor is connected not to an output of the supply voltage-lowering circuit but directly to an external power supply. A comparison is made between the voltage at the terminal of the driver MOS transistor connected to a large-capacity capacity load and an output of the supply voltage-lowering circuit, i.e., an internal supply voltage of the chip. On the basis of the result of comparison, the gate potential of the driver MOS transistor is controlled, and the large-capacity load is charged to the level of the internal supply voltage of the chip. Hence, only one driver transistor can be used as conventionally required two driver transistors connecting the external power supply and the large-capacity load, so that the chip area can be reduced. In addition, since the large-capacity load is directly connected to the external power supply, it is possible to stably maintain the operation of the supply voltage-lowering circuit and the potential of the internal supply voltage which is its output. Hence, it is possible to prevent the malfunctioning of the chip and a decline in the operating margin due to fluctations in the internal supply voltage. Since a control circuit can be deactivated upon completion of charging the large-capacity load, a reduction in power consumption can be attained.
摘要翻译：在使用电源降压电路的半导体芯片中的MOS型充电电路中，驱动器MOS晶体管不连接到电源降压电路的输出而是直接连接到外部电源。比较连接到大容量负载的驱动器MOS晶体管的端子与电源电压降低电路的输出之间的电压，即芯片的内部电源电压。基于比较结果，控制驱动器MOS晶体管的栅极电位，并将大容量负载充电到芯片的内部电源电压的电平。因此，只要使用一个驱动晶体管作为常规要求的连接外部电源和大容量负载的两个驱动晶体管，从而可以减小芯片面积。此外，由于大容量负载直接连接到外部电源，因此可以稳定地维持电源电压降低电路的操作和作为其输出的内部电源电压的电位。因此，可以防止芯片的故障和由于内部电源电压的波动引起的工作裕度的下降。由于在完成对大容量负载的充电时能够使控制电路停用，所以能够实现功耗的降低。

6. 发明授权

US5060194A Semiconductor memory device having a BICMOS memory cell 失效
标题翻译：具有BICMOS存储器单元的半导体存储器件
公开(公告)号：US5060194A
公开(公告)日：1991-10-22
申请号：US501865
申请日：1990-03-28
申请人： Koji Sakui , Tsuneaki Fuse , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
发明人： Koji Sakui , Tsuneaki Fuse , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
IPC分类号： G11C11/404 , G11C11/411 , G11C11/412 , H01L27/108
CPC分类号： H01L27/108 , G11C11/404 , G11C11/4113 , G11C11/412
摘要： A semiconductor memory device includes a plurality of memory cells each having a bipolar transistor whose collector-emitter voltage V.sub.CE is controlled according to the base potential to satisfy the condition of I.sub.BE

7. 再颁专利

USRE36993E Dynamic random access memory device with the combined open/folded bit-line pair arrangement 失效
标题翻译：具有组合打开/折叠位线对布置的动态随机存取存储器件
公开(公告)号：USRE36993E
公开(公告)日：2000-12-19
申请号：US612443
申请日：1996-03-07
申请人： Daisaburo Takashima , Shigeyoshi Watanabe
发明人： Daisaburo Takashima , Shigeyoshi Watanabe
IPC分类号： G11C11/401 , G11C7/18 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/18 , G11C11/4097 , H01L27/10805
摘要： A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.
摘要翻译：动态随机存取存储器件包括半导体衬底，衬底上的多个平行字线以及与衬底上的字线横向的多对位线。在字线和位线之间限定的交叉点选择性地布置单晶体管存储单元的阵列。该阵列被细分成多个子阵列部分。感测放大器部分连接到位线。读出放大器部分包括第一和第二读出放大器电路。位线的相邻位线对包括第一位线对和第二位线对，其中一个具有折叠位线布置，其包括在要连接到第一读出放大器电路的某个子阵列部分中并且另一个具有延伸到子阵列部分和与其相邻的另一个子阵列部分的开放位线布置，并且连接到第二读出放大器电路。

8. 发明授权

US5555519A Dynamic random access memory device with the combined open/folded bit-line pair arrangement 失效
公开(公告)号：US5555519A
公开(公告)日：1996-09-10
申请号：US348068
申请日：1994-11-23
申请人： Daisaburo Takashima , Shigeyoshi Watanabe
发明人： Daisaburo Takashima , Shigeyoshi Watanabe
IPC分类号： G11C11/401 , G11C7/18 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/18 , G11C11/4097 , H01L27/10805
摘要： A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.

9. 发明授权

US5416350A Semiconductor device with vertical transistors connected in series between bit lines 失效
标题翻译：具有垂直晶体管的半导体器件串联在位线之间
公开(公告)号：US5416350A
公开(公告)日：1995-05-16
申请号：US212774
申请日：1994-03-15
申请人： Shigeyoshi Watanabe
发明人： Shigeyoshi Watanabe
IPC分类号： H01L27/04 , G11C11/401 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/26
CPC分类号： H01L29/7827 , H01L27/10841
摘要： A semiconductor device connected between first and second wiring lines comprises a semiconductor substrate, a first semiconductor column formed by etching the substrate by a predetermined depth, a second semiconductor column formed by etching the substrate by a predetermined depth, with a predetermined distance set from the first semiconductor column, a first gate electrode formed around a side wall of the first semiconductor column with an insulating layer interposed, a second gate electrode formed around a side wall of the second semiconductor column with an insulating layer interposed, a first diffusion layer functioning as one of a source and a drain, the first diffusion layer being formed at a top portion of the first semiconductor column and connected to the first wiring line, a second diffusion layer functioning as another of the source and the drain, the second diffusion layer being formed at a top portion of the second semiconductor column and connected to the second wiring line, and a diffusion layer functioning as one of a source and a drain, the diffusion layer being formed at bottom portions and peripheral portions of the bottom portions of the first and second semiconductor columns and shared by the first and second semiconductor columns.
摘要翻译：连接在第一和第二布线之间的半导体器件包括半导体衬底，通过将衬底蚀刻预定深度形成的第一半导体柱，通过以预定深度蚀刻衬底而形成的第二半导体柱，第一半导体柱，在第一半导体柱的侧壁周围形成绝缘层的第一栅电极，插入有绝缘层的第二半导体柱侧壁上形成的第二栅电极，第一扩散层作为源极和漏极之一，第一扩散层形成在第一半导体柱的顶部并连接到第一布线，第二扩散层用作源极和漏极中的另一个，第二扩散层为形成在第二半导体柱的顶部并连接到第二布线li 以及用作源极和漏极之一的扩散层，所述扩散层形成在第一和第二半导体柱的底部的底部和周边部分处，并由第一和第二半导体柱共享。

10. 发明授权

US4996669A Electrically erasable programmable read-only memory with NAND memory cell structure 失效
标题翻译：具有NAND存储单元结构的电可擦除可编程只读存储器
公开(公告)号：US4996669A
公开(公告)日：1991-02-26
申请号：US489967
申请日：1990-03-07
申请人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
发明人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.
摘要翻译：具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。每个晶体管都有一个浮动栅极和一个控制栅极。并行字线连接到单元晶体管的控制栅极。在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极存储单元晶体管。

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