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1. 发明授权

US5088060A Electrically erasable programmable read-only memory with NAND memory cell structure 失效
标题翻译：具有NAND存储单元结构的电可擦除可编程只读存储器
公开(公告)号：US5088060A
公开(公告)日：1992-02-11
申请号：US634325
申请日：1990-12-26
申请人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
发明人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.
摘要翻译：具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。每个晶体管都有一个浮动栅极和一个控制栅极。并行字线连接到单元晶体管的控制栅极。在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极存储单元晶体管。

2. 发明授权

US4996669A Electrically erasable programmable read-only memory with NAND memory cell structure 失效
标题翻译：具有NAND存储单元结构的电可擦除可编程只读存储器
公开(公告)号：US4996669A
公开(公告)日：1991-02-26
申请号：US489967
申请日：1990-03-07
申请人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
发明人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.
摘要翻译：具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。每个晶体管都有一个浮动栅极和一个控制栅极。并行字线连接到单元晶体管的控制栅极。在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极存储单元晶体管。

3. 发明授权

US5179427A Non-volatile semiconductor memory device with voltage stabilizing electrode 失效
标题翻译：具有稳压电极的非易失性半导体存储器件
公开(公告)号：US5179427A
公开(公告)日：1993-01-12
申请号：US869123
申请日：1992-04-15
申请人： Ryozo Nakayama , Riichiro Shirota , Yasuo Itoh , Ryouhei Kirisawa , Hideko Odaira , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Seiichi Aritome , Tetsuo Endoh , Fujio Masuoka
发明人： Ryozo Nakayama , Riichiro Shirota , Yasuo Itoh , Ryouhei Kirisawa , Hideko Odaira , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Seiichi Aritome , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483
摘要： A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.
摘要翻译： NAND单元型EEPROM具有形成在衬底上的并行数据传输线，以及存储单元部分，其包括与位线的某个位线相关联的NAND型单元单元的多个NAND型单元单元。该NAND型单元单元具有预选数量的具有控制栅极的数据存储晶体管和选择晶体管的串联电路。衬底电压稳定层被绝缘地设置在衬底之上并且位于与某一位线相邻的场区中。导电层通过接触部分连接到基板，使得在对NAND型单元单元进行写入和擦除模式期间，基板电压可以恒定地设定为固定值的预选电压电位。

4. 发明授权

US5508957A Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through 失效
标题翻译：具有NAND单元结构的非易失性半导体存储器和具有不同通道长度的开关晶体管以减少穿通
公开(公告)号：US5508957A
公开(公告)日：1996-04-16
申请号：US312072
申请日：1994-09-26
申请人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/115 , G11C16/06 , H01L29/788
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/10 , G11C16/16 , H01L27/115
摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.
摘要翻译：具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管晶体管和地。每个单元晶体管具有浮置栅极和控制栅极。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元。用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

5. 发明授权

US5523980A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5523980A
公开(公告)日：1996-06-04
申请号：US364990
申请日：1994-12-28
申请人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
发明人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
IPC分类号： G11C16/06 , G11C8/12 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/34 , H01L29/78 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0483
摘要： A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines. A plurality of block-address latch circuits are provided to correspond to the selecting gate drivers, respectively, for temporarily storing signals derived from a row address by the row decoder, thereby to select at least two of the selecting gate drivers at the same time in order to write data.
摘要翻译：具有多个位线的NAND单元型EEPROM，与位线相交的多个控制栅极线，以及通过向控制栅极线施加电位而驱动的多个存储单元，用于选择性地存储数据，向位线和从其接收数据。存储单元形成多个单元单元。构成每个单元单元的存储单元通过公共选择栅极晶体管串联连接到一个位线。分别在位线上提供多个数据锁存电路，用于存储要写入由控制栅极线选择的存储单元的数据。此外，分别提供多个选择栅极驱动器以对应于用于驱动控制栅极线的单元单元。行解码器解码用于驱动选择栅极驱动器和控制栅极线的行地址。提供多个块地址锁存电路以分别对应于选择栅极驱动器，用于临时存储由行解码器从行地址导出的信号，从而同时选择至少两个选择栅极驱动器命令写数据。

6. 发明授权

US5978265A Non-volatile semiconductor memory device with nand type memory cell arrays 失效
标题翻译：具有n型存储单元阵列的非易失性半导体存储器件
公开(公告)号：US5978265A
公开(公告)日：1999-11-02
申请号：US746176
申请日：1991-08-15
申请人： Ryouhei Kirisawa , Riichiro Shirota , Ryozo Nakayama , Seiichi Aritome , Masaki Momodomi , Yasuo Itoh , Fujio Masuoka
发明人： Ryouhei Kirisawa , Riichiro Shirota , Ryozo Nakayama , Seiichi Aritome , Masaki Momodomi , Yasuo Itoh , Fujio Masuoka
IPC分类号： G11C17/12 , G11C16/04 , G11C16/10 , G11C17/00 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.
摘要翻译：公开了一种电可擦除可编程只读存储器，其具有连接到设置在半导体衬底上的并行位线的可编程存储器单元。存储单元包括NAND单元块，每个NAND单元具有存储单元晶体管的串联阵列。并行字线分别连接到存储单元晶体管的控制栅极。在数据写入模式中，包括所选择的存储单元的某个NAND单元块中的选择晶体管被导通以将特定单元块连接到与其相关联的相应位线。在这种条件下，电子被隧道注入到所选择的存储单元晶体管的浮动栅极中，并且特定晶体管的阈值增加到正值。因此，逻辑数据被写入所选择的存储单元晶体管中。通过将其浮置栅极中累积的载流子放电到其漏极或衬底来擦除所选择的单元晶体管中的数据，使得某个晶体管的阈值降低为负值。

7. 发明授权

US5453955A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5453955A
公开(公告)日：1995-09-26
申请号：US255904
申请日：1994-06-07
申请人： Koji Sakui , Hiroshi Nakamura , Masaki Momodomi , Riichiro Shirota , Fujio Masuoka
发明人： Koji Sakui , Hiroshi Nakamura , Masaki Momodomi , Riichiro Shirota , Fujio Masuoka
IPC分类号： G11C16/02 , G11C7/12 , G11C16/06 , G11C16/26 , G11C7/00
CPC分类号： G11C7/12 , G11C16/26
摘要： A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.
摘要翻译：非挥发性半导体存储器件包括用于将位线设置在预定读取电位以执行数据读取操作的读取充电晶体管，并且在读取操作期间读取用于将未选择的位线设置为接地电位的放电晶体管。这些晶体管由不同的控制信号控制，通过根据输入地址对每隔一个位线检测地址变化而获得，使得读出的放电晶体管保持导通，以将未选择的位线设置在地电位之前，在数据读取操作期间。

8. 再颁专利

USRE35838E Electrically erasable programmable read-only memory with NAND cell structure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：USRE35838E
公开(公告)日：1998-07-07
申请号：US430271
申请日：1995-04-28
申请人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
IPC分类号： G11C16/16 , G11C17/00
CPC分类号： G11C16/16
摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.
摘要翻译：公开了具有NAND单元结构的可擦除可编程只读存储器，其具有设置在N型衬底上的存储单元。存储器单元被分成NAND单元块，每个单元块具有存储单元晶体管的串联阵列。每个晶体管具有浮置栅极，连接到字线的控制栅极和用作其源极和漏极的N型扩散层。这些半导体层形成在形成于基板的表面区域的P型阱层中。阱层用作表面击穿防止层。在数据擦除模式期间，存储在所有存储单元中的数据同时被擦除。在擦除模式之后的数据写入模式期间，当选择某个NAND单元块时，NAND单元块中的存储单元依次进行数据写入。当数据被写入所选择的NAND单元块中的某个存储单元中时，该特定存储单元的控制栅极被提供有如此高的电压，以形成强电场，以允许在浮置栅极的存储单元和阱层。因此，只能选择所选单元格。

9. 发明授权

US5050125A Electrically erasable programmable read-only memory with NAND cellstructure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：US5050125A
公开(公告)日：1991-09-17
申请号：US272404
申请日：1988-11-17
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V）字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

10. 发明授权

US5440509A Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines 失效
标题翻译：电可擦除可编程只读存储器，NAND单元结构和中间电平电压最初应用于位线
公开(公告)号：US5440509A
公开(公告)日：1995-08-08
申请号：US22392
申请日：1993-02-24
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/115
摘要： An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有NAND单元结构的可擦除可编程只读存储器（EPROM）包括NAND单元块，每个单元块具有连接到相应位线的选择晶体管和串联连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供一种控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约0V），对位于第一个单元之间的字线或字线施加“H”电平电压（大约20V）选择字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入到特定位线的数据相对应的电压，以及在“H”和“L”电平电压之间施加中间电压到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

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