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1. 发明授权

US5892724A NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines 失效
标题翻译： NAND型动态RAM具有耦合到多开位线的临时存储寄存器和读出放大器
公开(公告)号：US5892724A
公开(公告)日：1999-04-06
申请号：US848152
申请日：1997-04-29
申请人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
发明人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
IPC分类号： G11C7/10 , G11C11/404 , G11C11/4096 , G11C11/4097 , G11C8/00
CPC分类号： G11C7/106 , G11C11/4045 , G11C11/4096 , G11C11/4097 , G11C7/1051 , G11C7/1078
摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.
摘要翻译：读出放大器连接在存储单元阵列之间，重写寄存器与读出放大器相邻地布置，第一传输门设置在读出放大器和存储单元阵列之间，第二传输门提供在存储单元的位线之间阵列和全局位线，以及用于控制传输门的栅极控制电路。当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

2. 发明授权

US5625602A NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines 失效
标题翻译： NAND型动态RAM具有耦合到多开位线的临时存储寄存器和读出放大器
公开(公告)号：US5625602A
公开(公告)日：1997-04-29
申请号：US446291
申请日：1995-05-22
申请人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
发明人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
IPC分类号： G11C7/10 , G11C11/404 , G11C11/4096 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/106 , G11C11/4045 , G11C11/4096 , G11C11/4097 , G11C7/1051 , G11C7/1078
摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.
摘要翻译：读出放大器连接在存储单元阵列之间，重写寄存器布置在与读出放大器相邻的位置，传输门设置在读出放大器和存储单元阵列之间，传输门提供在存储单元的位线之间阵列和全局位线，以及用于控制传输门的栅极控制电路。当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

3. 发明授权

US5717625A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5717625A
公开(公告)日：1998-02-10
申请号：US784963
申请日：1997-01-16
申请人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
发明人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
IPC分类号： G11C8/08 , G11C11/404 , G11C15/00
CPC分类号： G11C8/08 , G11C11/4045
摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.
摘要翻译：在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

4. 发明授权

US5418750A Semiconductor memory device for suppressing noises occurring on bit and word lines 失效
标题翻译：用于抑制位和字线上发生的噪声的半导体存储器件
公开(公告)号：US5418750A
公开(公告)日：1995-05-23
申请号：US200107
申请日：1994-02-22
申请人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
发明人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
IPC分类号： G11C11/407 , G11C11/405 , G11C11/4091 , G11C11/4096 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.
摘要翻译：半导体存储器件包括一系列存储器单元，分别连接到存储器单元的一系列位线，一系列读出放大器，连接到包括一系列位线的预定数量位线的相应位线组，用于读取连接到位线组的位线的存储器单元的输出数据，位线组包括至少相邻的第一和第二位线组，分配在位线和读出放大器之间并具有门的至少第一和第二晶体管，用于选择性地连接位线和读出放大器，以及一系列控制信号线，共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管，使得连接到第一位线组的第一晶体管第一位线组在一个方向上规则地排列，第二晶体管连接到第二位线组第一位线组以相反的方向规则地布置。

5. 发明授权

US06292390B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06292390B1
公开(公告)日：2001-09-18
申请号：US09755143
申请日：2001-01-08
申请人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
发明人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： G11C1134
CPC分类号： H01L27/1025 , G11C11/39 , H01L29/36 , H01L29/42304 , H01L29/456 , H01L29/73 , H01L29/7322 , H01L29/885 , H03F3/04 , H03K3/021 , H03K17/567
摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE
摘要翻译：半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

6. 发明授权

US5038191A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5038191A
公开(公告)日：1991-08-06
申请号：US486842
申请日：1990-03-01
申请人： Takehiro Hasegawa , Koji Sakui , Shigeyoshi Watanabe , Fujio Masuoka
发明人： Takehiro Hasegawa , Koji Sakui , Shigeyoshi Watanabe , Fujio Masuoka
IPC分类号： G11C11/41 , G11C11/401 , G11C11/404 , G11C11/411 , G11C11/412 , H01L21/331 , H01L21/8229 , H01L27/102 , H01L29/73 , H01L29/732
CPC分类号： G11C11/4113 , G11C11/404 , G11C11/412
摘要： A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing.
摘要翻译：半导体存储器件包括存储器阵列，其包括以矩阵形式布置的多个存储器单元，排列成列的多个字线和排成行的多个位线。每个存储单元包括双极晶体管，其中控制集电极 - 发射极电压，使得基极电流变化的极性根据基极 - 发射极电压的增加而改变，并且开关元件设置在基极双极晶体管和相关联的位线，并且可由相关联的字线控制。提供一种开关电路，用于在第二状态下将集电极电压施加到双极晶体管的集电极，在第二状态下，相关联的一个存储单元保持数据而不是相关联的存储单元可访问用于数据读取和数据的第二状态写作。

7. 发明授权

US06232822B1 Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism 失效
标题翻译：半导体器件包括被偏置以通过冲击电离机制产生负的基极电流的双极晶体管
公开(公告)号：US06232822B1
公开(公告)日：2001-05-15
申请号：US08268728
申请日：1994-06-30
申请人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
发明人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： H03K17687
CPC分类号： H01L27/1025 , G11C11/39 , H01L29/36 , H01L29/42304 , H01L29/456 , H01L29/73 , H01L29/7322 , H01L29/885 , H03F3/04 , H03K3/021 , H03K17/567
摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE
摘要翻译：半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

8. 发明授权

US5467303A Semiconductor memory device having register groups for writing and reading data 失效
标题翻译：具有用于写入和读取数据的寄存器组的半导体存储器件
公开(公告)号：US5467303A
公开(公告)日：1995-11-14
申请号：US380443
申请日：1995-01-30
申请人： Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
发明人： Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
IPC分类号： G11C11/405 , G11C11/401 , G11C11/404 , G11C11/4096 , G11C11/24 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/404
摘要： A semiconductor memory device comprises an array of memory cell units, each of which has a plurality of MOS transistors connected in series and a plurality of information storage capacitors corresponding in number to the MOS transistors and each having its one end connected to the source of a corresponding one of the MOS transistors, and a plurality of register groups each of which is adapted to temporarily store information stored in one of the memory cell units for each column of the array in order to read from and write into each memory cell unit.
摘要翻译：半导体存储器件包括一组存储单元单元，每个存储单元单元具有串联连接的多个MOS晶体管和多个与MOS晶体管相对应的多个信息存储电容器，每个信号存储电容器的一端连接到对应的一个MOS晶体管，以及多个寄存器组，每个寄存器组适于临时存储存储在阵列的每列的存储单元单元之一中的信息，以便从每个存储单元单元读取和写入。

9. 发明授权

US5060194A Semiconductor memory device having a BICMOS memory cell 失效
标题翻译：具有BICMOS存储器单元的半导体存储器件
公开(公告)号：US5060194A
公开(公告)日：1991-10-22
申请号：US501865
申请日：1990-03-28
申请人： Koji Sakui , Tsuneaki Fuse , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
发明人： Koji Sakui , Tsuneaki Fuse , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
IPC分类号： G11C11/404 , G11C11/411 , G11C11/412 , H01L27/108
CPC分类号： H01L27/108 , G11C11/404 , G11C11/4113 , G11C11/412
摘要： A semiconductor memory device includes a plurality of memory cells each having a bipolar transistor whose collector-emitter voltage V.sub.CE is controlled according to the base potential to satisfy the condition of I.sub.BE

10. 发明授权

US5463577A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5463577A
公开(公告)日：1995-10-31
申请号：US365104
申请日：1994-12-28
申请人： Yukihito Oowaki , Takehiro Hasegawa
发明人： Yukihito Oowaki , Takehiro Hasegawa
IPC分类号： G11C11/41 , G11C8/12 , G11C8/14 , G11C11/22 , G11C11/401 , G11C11/404 , G11C11/407 , G11C11/24
CPC分类号： G11C8/12 , G11C8/14
摘要： There is provided a semiconductor memory having a reduced power consumption in data access and a high access speed in a NAND cell array scheme in which a memory cell unit is constituted by cascade-connecting a plurality of memory cells with each other. A memory cell array is divided into a plurality of sub-arrays, and the divided sub-arrays are selectively activated, thereby decreasing the capacitances of the word lines, register word lines, bit lines, and the like which are charged/discharged in data access.
摘要翻译：提供了一种在NAND单元阵列方案中数据访问中具有降低的功耗以及高存取速度的半导体存储器，其中通过将多个存储单元彼此级联连接而构成存储单元单元。存储单元阵列被分成多个子阵列，并且分割的子阵列被选择性地激活，从而减少在数据中被充电/放电的字线，寄存器字线，位线等的电容访问。

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