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1. 发明授权

US06671838B1 Method and apparatus for programmable LBIST channel weighting 有权
标题翻译：用于可编程LBIST通道加权的方法和装置
公开(公告)号：US06671838B1
公开(公告)日：2003-12-30
申请号：US09671413
申请日：2000-09-27
申请人： Timothy J. Koprowski , Mary P. Kusko , Lawrence K. Lange , Bryan J. Robbins
发明人： Timothy J. Koprowski , Mary P. Kusko , Lawrence K. Lange , Bryan J. Robbins
IPC分类号： G11C2900
CPC分类号： G06F11/27 , G01R31/31835 , G01R31/318385 , G01R31/318547
摘要： An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.
摘要翻译：本发明的示例性实施例是用于测试集成电路上的逻辑电路的内置自检（BIST）方法和装置。随机测试图案数据由随机图案生成器生成。随机阻抗故障分析（RRFA）程序用于确定每个通道的加权要求，用于测试逻辑电路。来自RRFA程序的权重要求应用于随机测试模式数据，从而产生加权测试模式数据。加权测试图案数据然后可编程地应用于扫描链。

2. 发明授权

US06442720B1 Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis 失效
标题翻译：降低半导体芯片红外成像曝光时间的技术进行故障分析
公开(公告)号：US06442720B1
公开(公告)日：2002-08-27
申请号：US09326226
申请日：1999-06-04
申请人： Timothy J. Koprowski , Mary P. Kusko , Richard F. Rizzolo , Peilin Song
发明人： Timothy J. Koprowski , Mary P. Kusko , Richard F. Rizzolo , Peilin Song
IPC分类号： G01R3128
CPC分类号： G01R31/31858
摘要： The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, and observing an exercised failing circuit. The invention can include the use of PICA techniques to observe the exercised failing circuit. In another embodiment, the invention can include using LBIST or a WRP technique to search for the failing pattern. In yet another it includes the step of using an algorithm to exercise the exercised failing circuit. In another embodiment, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern. The algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern. In one embodiment, one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict. In another embodiment the method further includes the step of using an algorithm to densify the pattern set.
摘要翻译：本发明可以包括用于测试IC芯片的方法和系统，包括以下步骤：对第一故障模式执行二进制搜索，确定故障接收器锁存器，执行后锥迹线以确定所有源锁存器，确定源锁存器逻辑状态将源锁存器逻辑状态定位在扫描链中，通过在没有系统L1时钟的情况下在源锁存器上施加逻辑转换并观察行使的故障电路来执行芯片扫描路径。本发明可以包括使用PICA技术来观察行使的故障电路。在另一个实施例中，本发明可以包括使用LBIST或WRP技术来搜索失败的模式。在另一方面，它包括使用算法来锻炼锻炼的故障电路的步骤。在另一个实施例中，该方法包括创建要被扫描的网络图案的步骤，包括导致执行故障电路的原始图案的和以及原始图案的一个或多个偏移版本。该算法可以包括一个步骤，其中移位版本中的一个被移位了多个时钟，其中时钟数等于原始图案的长度。在一个实施例中，移位版本中的一个被移位了多个时钟，其中选择时钟的数量，使得原始模式和移位版本之一的总和不会引起扫描冲突。在另一个实施例中，该方法还包括使用算法来密集模式集的步骤。

3. 发明授权

US06708305B1 Deterministic random LBIST 失效
标题翻译：确定性随机LBIST
公开(公告)号：US06708305B1
公开(公告)日：2004-03-16
申请号：US09691370
申请日：2000-10-18
申请人： L. Owen Farnsworth , Brion L. Keller , Bernd K. Koenemann , Timothy J. Koprowski , Thomas J. Snethen , Donald L. Wheater
发明人： L. Owen Farnsworth , Brion L. Keller , Bernd K. Koenemann , Timothy J. Koprowski , Thomas J. Snethen , Donald L. Wheater
IPC分类号： G01R3128
CPC分类号： G01R31/318594 , G01R31/318552
摘要： Deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment tests one or more logic devices.
摘要翻译：公开了通过使用随机LBIST应用确定性存储模式测试（DSPT）的确定性随机逻辑内置自检（LBIST）。基本上，本发明选择适用于需要关心位的扫描周期使用的伪随机模式。扫描周期可能是当前或将来的扫描周期。特别地，本发明确定特定扫描周期的护理位。生成伪随机模式，然后将其与特定的扫描周期对准。如果伪随机模式包含护理位，具有正确的值并且在模式内的适当位置，则该对准测试一个或多个逻辑器件。

4. 发明授权

US6125465A Isolation/removal of faults during LBIST testing 失效
标题翻译：在LBIST测试期间隔离/去除故障
公开(公告)号：US6125465A
公开(公告)日：2000-09-26
申请号：US4873
申请日：1998-01-09
申请人： Timothy G. McNamara , William V. Huott , Timothy J. Koprowski
发明人： Timothy G. McNamara , William V. Huott , Timothy J. Koprowski
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318552
摘要： A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches can be set such that the L1 cache will no longer receive system clocks during LBIST testing. Logic causing an intermittent failure will no longer receive system clocks and hence will no longer cause intermittent LBIST signatures. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. Generally, a chip, has a basic clock distribution and control system that the chip is divided into a number (N) of functional units with each unit receiving system clocks from its own clock control macro. Each clock control macro receives an oscillator signal and a bit from the GPTR (General Purpose Test Register). All the functional units contain latches that are connected into one scan chain.
摘要翻译：整个芯片（即所有逻辑和阵列正在获得系统时钟）的LBIST测试的方法使得能够在诸如L1高速缓存的区域中发现间歇性故障。可以设置诸如GPTR锁存器的锁存器，使得L1缓存在LBIST测试期间将不再接收系统时钟。导致间歇性故障的逻辑将不再接收系统时钟，因此不再会导致间歇性LBIST签名。 LBIST测试可以继续寻找下一个故障，如果存在，或证明剩余的逻辑不包含故障。通常，芯片具有基本的时钟分配和控制系统，该芯片被分成多个（N个）功能单元，每个单元从其自己的时钟控制宏接收系统时钟。每个时钟控制宏从GPTR（通用测试寄存器）接收振荡器信号和位。所有功能单元都包含连接到一个扫描链中的锁存器。

5. 发明授权

US06816990B2 VLSI chip test power reduction 失效
标题翻译： VLSI芯片测试功耗降低
公开(公告)号：US06816990B2
公开(公告)日：2004-11-09
申请号：US10058485
申请日：2002-01-28
申请人： Peilin Song , Timothy J. Koprowski , Ulrich Baur , Franco Motika
发明人： Peilin Song , Timothy J. Koprowski , Ulrich Baur , Franco Motika
IPC分类号： G01R3128
CPC分类号： G01R31/31721 , G01R31/31707 , G01R31/318307 , G01R31/318502 , G01R31/318522 , G01R31/3187
摘要： LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.
摘要翻译： LBIST和加权LBIST测试在测试对象的不同部分上同时进行。这种新的测试方法和设计变化与传统的测试策略相比，测试覆盖率和测试时间都大大降低。它可以应用于晶圆，芯片，MCM和系统测试级别。最重要的是，它不需要新的支持工具。当前的测试软件将与传统的测试策略一样工作。在相同测试会话中调度LBIST和加权LBIST测试降低了整体功耗，因为加权LBIST测试比平面LBIST测试消耗的功率少得多。在相同的测试会话中，如果使用加权LBIST测试逻辑的某些部分，而使用LBIST测试其他部分，则电路元件在任何给定时间消耗的功率降低。

6. 发明授权

US06629281B1 Method and system for at speed diagnostics and bit fail mapping 失效
标题翻译：用于速度诊断和位故障映射的方法和系统
公开(公告)号：US06629281B1
公开(公告)日：2003-09-30
申请号：US09669917
申请日：2000-09-26
申请人： Timothy G. McNamara , William V. Huott , Timothy J. Koprowski
发明人： Timothy G. McNamara , William V. Huott , Timothy J. Koprowski
IPC分类号： G11C2900
CPC分类号： G11C29/12015 , G01R31/3187 , G11C29/14 , G11C29/44 , G11C2029/1206 , G11C2029/1208
摘要： This invention describes a method and apparatus, contained within an integrated circuit, for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST). A programmable clock counter, on the integrated circuit, stores a specified number of clock cycles and sends a signal to stop a BIST engine once the specified number of clock cycles have been generated. The intermediate results can then be mapped bit by bit in order to isolate the cause of failure.
摘要翻译：本发明描述了一种包含在集成电路内的方法和装置，用于通过精确地控制在内置自检（BIST）期间施加的时钟数来隔离故障。在集成电路上的可编程时钟计数器存储指定数量的时钟周期，并在生成指定数量的时钟周期后发送一个信号来停止BIST引擎。然后可以逐个映射中间结果，以隔离故障原因。

7. 发明授权

US06327685B1 Logic built-in self test 有权
标题翻译：逻辑内置自检
公开(公告)号：US06327685B1
公开(公告)日：2001-12-04
申请号：US09310444
申请日：1999-05-12
申请人： Timothy J. Koprowski , Franco Motika
发明人： Timothy J. Koprowski , Franco Motika
IPC分类号： G01R3128
CPC分类号： G01R31/3181
摘要： A BIST method that modifies the scan chain path and scan clocks to allow for distributed BIST test. In this distributed BIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple Input Signature Register (MISR) are combined as an integral part of the scan chain, and each scan cycle is utilized as a test cycle.
摘要翻译： BIST方法修改扫描链路和扫描时钟以允许分布式BIST测试。在这种分布式BIST概念中，线性反馈移位寄存器（LFSR）和多输入签名寄存器（MISR）被组合为扫描链的组成部分，并且每个扫描周期被用作测试周期。

8. 发明授权

US06968489B2 Pseudo random optimized built-in self-test 有权
标题翻译：伪随机优化内置自检
公开(公告)号：US06968489B2
公开(公告)日：2005-11-22
申请号：US10055275
申请日：2002-01-23
申请人： Franco Motika , Timothy J. Koprowski
发明人： Franco Motika , Timothy J. Koprowski
IPC分类号： G01R31/3181 , G01R31/3185 , G01R31/28 , G06F11/00
CPC分类号： G01R31/318385 , G01R31/31813 , G01R31/318547
摘要： Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern generation with either internal or external weight set selection. WRP patterns are generated by a tester either externally or internally to a device under test (DUT) and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.
摘要翻译：平坦伪随机测试模式与加权伪随机测试模式相结合提供，以便可以在每个周期改变应用于LSSD移位寄存器（SR）链中的每个锁存器的权重。这使得片内加权模式生成与内部或外部权重集合选择的集成。 WRP模式由测试仪在外部或内部生成到被测器件（DUT），并通过移位寄存器输入（SRI或WPI）加载到芯片的移位寄存器锁存器（SRL）中。测试（或LSSD测试器循环序列）包括使用WRP加载SR链中的SRL，脉冲相应的时钟，并将在SRL中捕获的响应卸载到多输入签名寄存器（MISR）中。然后可以对每个权重集合多次应用每个测试，权重集为每个SRL分配权重因子或概率。

9. 发明授权

US06629280B1 Method and apparatus for delaying ABIST start 失效
标题翻译：延迟ABIST启动的方法和设备
公开(公告)号：US06629280B1
公开(公告)日：2003-09-30
申请号：US09669462
申请日：2000-09-25
申请人： Timothy J. Koprowski , William V. Huott , Timothy G. McNamara , Pradip Patel
发明人： Timothy J. Koprowski , William V. Huott , Timothy G. McNamara , Pradip Patel
IPC分类号： G01B3128
CPC分类号： G11C29/12015 , G11C29/14
摘要： An exemplary embodiment of the invention is a method and apparatus for delaying the start of an array built-in self-test (ABIST) until after the ABIST memory arrays have been started. The length of the delay is determined by the value in a programmable delay located on the integrated circuit. The initiation of the ABIST test is delayed by the time specified in the programmable delay.
摘要翻译：本发明的示例性实施例是一种用于在ABIST存储器阵列启动之后延迟阵列内置自检（ABIST）的启动的方法和装置。延迟的长度由位于集成电路上的可编程延迟中的值确定。 ABIST测试的启动延迟了可编程延迟中指定的时间。

10. 发明授权

US5479414A Look ahead pattern generation and simulation including support for parallel fault simulation in LSSD/VLSI logic circuit testing 失效
标题翻译：展望未来的模式生成和仿真，包括支持LSSD / VLSI逻辑电路测试中的并行故障仿真
公开(公告)号：US5479414A
公开(公告)日：1995-12-26
申请号：US215165
申请日：1994-03-07
申请人： Paul N. Keller , Timothy J. Koprowski
发明人： Paul N. Keller , Timothy J. Koprowski
IPC分类号： G01R31/28 , F02B75/02 , G01R31/3181 , G01R31/3183 , G01R31/319 , G06F11/22 , G06F17/50
CPC分类号： G01R31/318307 , G01R31/31813 , F02B2075/027 , G01R31/31919
摘要： Algorithmically generated test patterns are structured for efficient test of "scan path" logic devices. A look ahead pattern generation and simulation scheme achieves a pre-specified fault coverage. The fault simulation engine picks one of two paths at the end of each Tester Loop (TL) simulation: (1) restore to the state just prior to the current simulated Tester Loop and advance the pattern generators one state if an ineffective Tester Loop was found or (2) advance the pattern generators one state (from the end of the Tester Loop) if an effective Tester Loop was encountered. This basic technique can be modified to support parallel fault simulation by defining the pattern generator state at the start of the next tester loop (TL) state (TL.sub.n+1) to be one state advanced from the pattern generator state at the START of TL.sub.n. The pattern generator state for the start of all future TLs can be determined and parallel fault simulation is supported.
摘要翻译：结构化算法生成的测试模式用于“扫描路径”逻辑器件的有效测试。前瞻模式生成和模拟方案实现了预先指定的故障覆盖。故障模拟引擎在每个测试循环（TL）模拟结束时选择两条路径之一：（1）恢复到当前模拟的测试仪循环之前的状态，如果发现无效的测试仪循环，则将模式生成器推送到一个状态或者（2）如果遇到有效的测试仪循环，则将模式生成器推送一个状态（从测试仪循环的结尾）。可以通过将下一个测试器回路（TL）状态（TLn + 1）的起始处的模式发生器状态定义为在TLn的起始处从模式发生器状态提前的一个状态来修改该基本技术以支持并行故障模拟。可以确定所有未来TL的启动的模式发生器状态，并支持并行故障模拟。

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