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1. 发明授权

US06629280B1 Method and apparatus for delaying ABIST start 失效
标题翻译：延迟ABIST启动的方法和设备
公开(公告)号：US06629280B1
公开(公告)日：2003-09-30
申请号：US09669462
申请日：2000-09-25
申请人： Timothy J. Koprowski , William V. Huott , Timothy G. McNamara , Pradip Patel
发明人： Timothy J. Koprowski , William V. Huott , Timothy G. McNamara , Pradip Patel
IPC分类号： G01B3128
CPC分类号： G11C29/12015 , G11C29/14
摘要： An exemplary embodiment of the invention is a method and apparatus for delaying the start of an array built-in self-test (ABIST) until after the ABIST memory arrays have been started. The length of the delay is determined by the value in a programmable delay located on the integrated circuit. The initiation of the ABIST test is delayed by the time specified in the programmable delay.
摘要翻译：本发明的示例性实施例是一种用于在ABIST存储器阵列启动之后延迟阵列内置自检（ABIST）的启动的方法和装置。延迟的长度由位于集成电路上的可编程延迟中的值确定。 ABIST测试的启动延迟了可编程延迟中指定的时间。

2. 发明授权

US06363504B1 Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation 失效
标题翻译：用于在程序控制下在可选子集中同时或顺序测试一组多个芯片以限制芯片功率消耗的电子系统
公开(公告)号：US06363504B1
公开(公告)日：2002-03-26
申请号：US09386945
申请日：1999-08-31
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G01B3128
CPC分类号： G01R31/31926
摘要： A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal.
摘要翻译：用于测试集成电路芯片的系统包括产生时钟信号的信号发生器; 以及顺序控制电路，具有接收时钟信号的第一输入端，用于接收命令的第二输入端和多个输出端。命令源将命令的可编程序列发送到控制电路的第二输入; 并且作为响应，控制电路将来自第一输入的时钟信号传递到命令选择的某些输出。控制电路的所有输出通过相应的时钟发射器耦合到不同的待测试芯片; 并且因此响应于可编程命令，时钟信号以可选择的子集顺序发送到要测试的芯片。通过这样的排序，当芯片接收时钟信号时耗散大量功率的芯片可以调节被测试的芯片的总功耗，但是当它们没有接收到时钟时消耗大量的功率信号。

3. 发明授权

US06751767B1 Test pattern compression method, apparatus, system and storage medium 失效
标题翻译：测试图案压缩方法，设备，系统和存储介质
公开(公告)号：US06751767B1
公开(公告)日：2004-06-15
申请号：US09671368
申请日：2000-09-28
申请人： Tamaki Toumiya
发明人： Tamaki Toumiya
IPC分类号： G01B3128
CPC分类号： G06F11/261 , G06F11/263
摘要： A system and method for test pattern compression includes a local CPU for dividing faults into a plurality of fault groups, assigning the fault groups to respective remote CPUs, that are connected to the local CPU in parallel with each other. Each remote CPU generates test patterns having undefined values assigned to pins of the logic circuit that do not participate in fault detection. The local CPU acquires pluralities of test patterns of the remote CPUs, generates new test patterns obtained by merging those test patterns that have identical pattern numbers among the pluralities of test patterns, and attempts to merge these newly generated test patterns.
摘要翻译：用于测试模式压缩的系统和方法包括用于将故障分为多个故障组的本地CPU，将故障组分配给彼此并行连接到本地CPU的各个远程CPU。每个远程CPU产生具有分配给不参与故障检测的逻辑电路引脚的未定义值的测试模式。本地CPU获取多个远程CPU的测试模式，生成通过在多个测试模式中合并具有相同模式编号的测试模式获得的新测试模式，并尝试合并这些新生成的测试模式。

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