专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06442720B1 Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis 失效
标题翻译：降低半导体芯片红外成像曝光时间的技术进行故障分析
公开(公告)号：US06442720B1
公开(公告)日：2002-08-27
申请号：US09326226
申请日：1999-06-04
申请人： Timothy J. Koprowski , Mary P. Kusko , Richard F. Rizzolo , Peilin Song
发明人： Timothy J. Koprowski , Mary P. Kusko , Richard F. Rizzolo , Peilin Song
IPC分类号： G01R3128
CPC分类号： G01R31/31858
摘要： The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, and observing an exercised failing circuit. The invention can include the use of PICA techniques to observe the exercised failing circuit. In another embodiment, the invention can include using LBIST or a WRP technique to search for the failing pattern. In yet another it includes the step of using an algorithm to exercise the exercised failing circuit. In another embodiment, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern. The algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern. In one embodiment, one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict. In another embodiment the method further includes the step of using an algorithm to densify the pattern set.
摘要翻译：本发明可以包括用于测试IC芯片的方法和系统，包括以下步骤：对第一故障模式执行二进制搜索，确定故障接收器锁存器，执行后锥迹线以确定所有源锁存器，确定源锁存器逻辑状态将源锁存器逻辑状态定位在扫描链中，通过在没有系统L1时钟的情况下在源锁存器上施加逻辑转换并观察行使的故障电路来执行芯片扫描路径。本发明可以包括使用PICA技术来观察行使的故障电路。在另一个实施例中，本发明可以包括使用LBIST或WRP技术来搜索失败的模式。在另一方面，它包括使用算法来锻炼锻炼的故障电路的步骤。在另一个实施例中，该方法包括创建要被扫描的网络图案的步骤，包括导致执行故障电路的原始图案的和以及原始图案的一个或多个偏移版本。该算法可以包括一个步骤，其中移位版本中的一个被移位了多个时钟，其中时钟数等于原始图案的长度。在一个实施例中，移位版本中的一个被移位了多个时钟，其中选择时钟的数量，使得原始模式和移位版本之一的总和不会引起扫描冲突。在另一个实施例中，该方法还包括使用算法来密集模式集的步骤。

2. 发明授权

US06453436B1 Method and apparatus for improving transition fault testability of semiconductor chips 失效
标题翻译：改善半导体芯片的过渡故障可测性的方法和装置
公开(公告)号：US06453436B1
公开(公告)日：2002-09-17
申请号：US09473811
申请日：1999-12-28
申请人： Richard F. Rizzolo , Peilin Song
发明人： Richard F. Rizzolo , Peilin Song
IPC分类号： G01R3128
CPC分类号： G01R31/318525 , G01R31/31853 , G01R31/31858
摘要： A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch, a second shift register latch, and a third shift register latch. A first multiplexor is connected between the first and second shift register latches, and a second multiplexor is connected between the second and third shift register latches. Each multiplexor is configured for implementing a jump mode such that a logic value may be passed via the first multiplexor from the first shift register latch to the third shift register latch.
摘要翻译：提供扫描链锁存电路。扫描链锁存电路包括第一移位寄存器锁存器，第二移位寄存器锁存器和第三移位寄存器锁存器。第一复用器连接在第一和第二移位寄存器锁存器之间，第二多路复用器连接在第二和第三移位寄存器锁存器之间。每个多路复用器被配置为实现跳跃模式，使得逻辑值可以经由第一多路复用器从第一移位寄存器锁存器传递到第三移位寄存器锁存器。

3. 发明授权

US06662324B1 Global transition scan based AC method 失效
标题翻译：基于全局过渡扫描的AC方法
公开(公告)号：US06662324B1
公开(公告)日：2003-12-09
申请号：US09642371
申请日：2000-08-21
申请人： Franco Motika , Richard F. Rizzolo , Peilin Song , William V. Huott , Ulrich Baur
发明人： Franco Motika , Richard F. Rizzolo , Peilin Song , William V. Huott , Ulrich Baur
IPC分类号： G01R3128
CPC分类号： G01R31/318525 , G01R31/31853 , G01R31/31858
摘要： The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather uses its current state as reference and switches to the opposite state. To accomplish this, a complement signal similar to a latch reset (i.e., reset-to-complement) can be used.
摘要翻译：本发明能够在不改变另一个状态的情况下补充移位寄存器锁存器（SRL）中的主（L1）或从锁存器（L2）的状态。当使用正常扫描链序列正确加载LSSD扫描链后，可以使用下一个系统时钟序列来启动扫描链中每个SRL所需的转换。补充LSSD扫描链中锁存器状态的实际机制可以根据L1或L2锁存器中的哪一个进行补充而变化; 实际扫描链和Shift Register Latch（SRL）设计的细节; 和半导体芯片电路技术。补充功能可以作为SRL设计的一个组成部分提供，对系统路径和性能影响最小。一种替代的补充方法是使用自补充锁存功能。在这种设计中，要补充的锁存器不需要包含补码值的附加输入，而是使用其当前状态作为参考，并切换到相反的状态。为了实现这一点，可以使用类似于锁存器复位（即，复位到补码）的补码信号。

4. 发明授权

US06490702B1 Scan structure for improving transition fault coverage and scan diagnostics 失效
标题翻译：用于改善过渡故障覆盖和扫描诊断的扫描结构
公开(公告)号：US06490702B1
公开(公告)日：2002-12-03
申请号：US09473810
申请日：1999-12-28
申请人： Peilin Song , Richard F. Rizzolo , Franco Motika , Ulrich W. Baur
发明人： Peilin Song , Richard F. Rizzolo , Franco Motika , Ulrich W. Baur
IPC分类号： G01R3128
CPC分类号： G01R31/318541
摘要： A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch and a second shift register latch. The scan chain latch circuit also includes a multiplexor connected between the first and second shift register latches, the multiplexor has a select line for controlling the function of the multiplexor. The multiplexor is configured for implementing an inverting mode such that a logic value may be passed via the multiplexor from the first shift register latch to the second shift register latch in one of a non-inverted state and an inverted state based upon the state of the select line.
摘要翻译：提供扫描链锁存电路。扫描链锁存电路包括第一移位寄存器锁存器和第二移位寄存器锁存器。扫描链锁存电路还包括连接在第一和第二移位寄存器锁存器之间的多路复用器，多路复用器具有用于控制多路复用器功能的选择线。多路复用器被配置为实现反相模式，使得逻辑值可以以非反相状态和反相状态中的一个从第一移位寄存器锁存器传递到第二移位寄存器锁存器，基于选择行。

5. 发明授权

US06751765B1 Method and system for determining repeatable yield detractors of integrated circuits 失效
标题翻译：用于确定集成电路的可重复产量剔除器的方法和系统
公开(公告)号：US06751765B1
公开(公告)日：2004-06-15
申请号：US09722880
申请日：2000-11-27
申请人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
发明人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
IPC分类号： G01R3128
CPC分类号： G01R31/3185
摘要： An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
摘要翻译：本发明的示例性实施例是用于LBIST测试集成电路的方法。该方法包括生成多个多位测试模式，并且通过多个测试模式分区对多位测试模式进行分组，所述多个测试模式分区包括具有第一数量位的第一测试模式分区和具有第二数量位的第二测试模式分区大于第一个数字。将第一测试模式分区应用于集成电路以生成与第一参考签名进行比较以检测故障的第一签名。将第二测试模式分区应用于集成电路以产生与第二参考签名进行比较的第二签名，以检测集成电路中的故障。

6. 发明授权

US5455931A Programmable clock tuning system and method 失效
标题翻译：可编程时钟调谐系统及方法
公开(公告)号：US5455931A
公开(公告)日：1995-10-03
申请号：US155178
申请日：1993-11-19
申请人： Peter J. Camporese , Patrick J. Meaney , Brian J. O'Leary , Richard F. Rizzolo
发明人： Peter J. Camporese , Patrick J. Meaney , Brian J. O'Leary , Richard F. Rizzolo
IPC分类号： G06F1/10 , G06F17/50 , G06F1/04
CPC分类号： G06F17/5031 , G06F1/10
摘要： A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.
摘要翻译：一种具有增强的定时故障诊断和非层次功能的数据处理系统的时钟调整系统和方法。通用和单独的相位调整功能均可确保分布在计算机系统中的时钟脉冲的可编程调谐，从而便于通过在逻辑路径之间移动时序余量来将定时裕度故障隔离到特定的时钟信号或增强系统性能。讨论了单时钟和双时钟数据处理以及每个时钟调整实施例。

7. 发明授权

US5142167A Encoding for simultaneous switching output noise reduction 失效
标题翻译：编码用于同时切换输出噪声降低
公开(公告)号：US5142167A
公开(公告)日：1992-08-25
申请号：US694178
申请日：1991-05-01
申请人： Joseph L. Temple , Richard F. Rizzolo , Charles B. Winn
发明人： Joseph L. Temple , Richard F. Rizzolo , Charles B. Winn
IPC分类号： G06F3/00 , G06F1/04 , H03K17/16 , H03K19/003 , H03M7/20 , H04B15/00
CPC分类号： H03M7/20 , H03K19/00346
摘要： This invention reduces the Delta I noise on an integrated circuit chip by reducing the changes in current supply required for transitions in logic states of the input/output devices. The invention uses a 3/6 binary code for communicating between integrated circuit chips. This code uses six bits to represent the 16 hex code digits typically used for computer instructions. Three of the six bits are in a high logic state and three of the six bits are in a low logic state for all 16 hex code representations. Therefore, changing from any one logic state to another, does not change the overall current supply required by the six input/output devices. Groups of six input/output devices (corresponding to the 3/6 code) are located relatively close to each other with respect to the power supply pins which supply current to the six input/output devices. As a result, there is a high to low transition for every low to high transition over similar parasitic impedances on the input/output devices. This leads to low Delta I noise because the noise created by individual transitions cancel each other out when viewed as a six device group. The high overhead pin count for a six digit code instead of the normal four digit code for hex representation is compensated for because input/output pins normally replaced by extra power supply pins (to reduce Delta I noise) can be used as input/output pins. Therefore, the 3/6 code frees up extra input/output pins when the Delta I noise would normally force those pins to be used for power supply.
摘要翻译：本发明通过减少输入/输出设备的逻辑状态中的转换所需的电流供应的变化来减小集成电路芯片上的ΔI噪声。本发明使用3/6二进制码在集成电路芯片之间进行通信。此代码使用六位来表示通常用于计算机指令的16位十六进制代码数字。六位中的三位处于高逻辑状态，对于所有16个十六进制代码表示，六位中的三位为低逻辑状态。因此，从任何一个逻辑状态变为另一个逻辑状态不会改变六个输入/输出设备所需的总电流供应。六个输入/输出设备（对应于3/6代码）的组相对于向六个输入/输出设备供电的电源引脚彼此相对靠近。因此，对于输入/输出设备上的类似寄生阻抗，每个低电平到高电平转换都有高到低的转换。这导致较低的Delta I噪声，因为当被视为六个器件组时，由各个转换产生的噪声彼此抵消。由于输入/输出引脚通常由额外的电源引脚替代（降低Delta I噪声），因此可以补偿六位数代码而不是用于十六进制表示的常规四位代码的高架空引脚数，可用作输入/输出引脚。因此，当Delta I噪声通常会迫使这些引脚用于供电时，3/6代码释放额外的输入/输出引脚。

8. 发明授权

US06971054B2 Method and system for determining repeatable yield detractors of integrated circuits 失效
标题翻译：用于确定集成电路的可重复产量剔除器的方法和系统
公开(公告)号：US06971054B2
公开(公告)日：2005-11-29
申请号：US10138992
申请日：2002-05-02
申请人： Raymond J. Kurtulik , Franco Motika , Richard F. Rizzolo
发明人： Raymond J. Kurtulik , Franco Motika , Richard F. Rizzolo
IPC分类号： G01R31/3185 , G01R31/28 , G11C29/00
CPC分类号： G01R31/3185
摘要： An exemplary embodiment of the present invention is a method for testing an integrated circuit. The method includes generating a test pattern and generating a reference signature corresponding to the test pattern. An integrated circuit test is executed in response to the test pattern and a result signature is generated in response to data output from executing the integrated circuit test. The result signature is compared to the reference signature and a current failing signature is created if the two don't match. The current failing signature is copy of the result signature. Common error analysis is executed in response to creating the current failing signature. Additional embodiments include a system and storage medium for testing an integrated circuit.
摘要翻译：本发明的示例性实施例是用于测试集成电路的方法。该方法包括生成测试图案并生成与测试图案相对应的参考签名。响应于测试模式执行集成电路测试，并且响应于执行集成电路测试的数据输出而产生结果签名。将结果签名与参考签名进行比较，如果两者不匹配，则创建当前失败的签名。当前失败的签名是结果签名的副本。响应于创建当前失败的签名执行常见错误分析。另外的实施例包括用于测试集成电路的系统和存储介质。

9. 发明授权

US4760289A Two-level differential cascode current switch masterslice 失效
标题翻译：两级差分共源共栅电流开关主机
公开(公告)号：US4760289A
公开(公告)日：1988-07-26
申请号：US893061
申请日：1986-08-04
申请人： Edward B. Eichelberger , Stephen E. Bello , Rolf O. Bergenn , William M. Chu , John A. Ludwig , Richard F. Rizzolo
发明人： Edward B. Eichelberger , Stephen E. Bello , Rolf O. Bergenn , William M. Chu , John A. Ludwig , Richard F. Rizzolo
IPC分类号： H03K19/086 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L23/528 , H01L27/118 , H03K17/60 , H03K17/62 , H03K19/173 , H03K19/21 , H03K19/177
CPC分类号： H01L23/528 , H01L27/11801 , H03K17/603 , H03K17/6264 , H03K19/1735 , H03K19/1738 , H03K19/212 , H01L2924/0002
摘要： A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite of increased wire due to differential logic, and potential increased complexity in design software, the invention is actually readily adaptable to existing masterslice design systems.
摘要翻译：一种主板单元，可用于形成任何选定的两组差分共源共栅电流开关基本电路的书集。与以相同功率运行的ECL主机电路相比，提供了20％的性能提升。尽管由于差分逻辑增加了电线，并且设计软件的潜在增加的复杂性，本发明实际上容易适应现有的主机设计系统。

10. 发明授权

US06532571B1 Method to improve a testability analysis of a hierarchical design 有权
标题翻译：提高分层设计可测性分析的方法
公开(公告)号：US06532571B1
公开(公告)日：2003-03-11
申请号：US09489240
申请日：2000-01-21
申请人： Richard M. Gabrielson , Kevin W. McCauley , Richard F. Rizzolo , Bryan J. Robbins , Joseph M. Swenton
发明人： Richard M. Gabrielson , Kevin W. McCauley , Richard F. Rizzolo , Bryan J. Robbins , Joseph M. Swenton
IPC分类号： G06F1750
CPC分类号： G01R31/318378 , G01R31/31835
摘要： A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip design. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying a logical description of a second portion of the semiconductor chip design and performing an RPT analysis on the second macro netlist. The first macro netlist is combined with the second macro netlist and an RPT analysis is performed on the combination of the first and second macro netlists.
摘要翻译：一种改进由多个宏形成的分层半导体芯片设计的可测试性和分析的方法，每个宏识别半导体芯片设计的特定部分。该方法包括提供识别半导体芯片设计的第一部分的逻辑描述并在第一宏网表上执行RPT分析的第一宏网表。该方法还包括提供识别半导体芯片设计的第二部分的逻辑描述并在第二宏网表上执行RPT分析的第二宏网表。第一个宏网表与第二个宏网表组合，并对第一个和第二个宏网表的组合进行RPT分析。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式