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1. 发明授权

US06708305B1 Deterministic random LBIST 失效
标题翻译：确定性随机LBIST
公开(公告)号：US06708305B1
公开(公告)日：2004-03-16
申请号：US09691370
申请日：2000-10-18
申请人： L. Owen Farnsworth , Brion L. Keller , Bernd K. Koenemann , Timothy J. Koprowski , Thomas J. Snethen , Donald L. Wheater
发明人： L. Owen Farnsworth , Brion L. Keller , Bernd K. Koenemann , Timothy J. Koprowski , Thomas J. Snethen , Donald L. Wheater
IPC分类号： G01R3128
CPC分类号： G01R31/318594 , G01R31/318552
摘要： Deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment tests one or more logic devices.
摘要翻译：公开了通过使用随机LBIST应用确定性存储模式测试（DSPT）的确定性随机逻辑内置自检（LBIST）。基本上，本发明选择适用于需要关心位的扫描周期使用的伪随机模式。扫描周期可能是当前或将来的扫描周期。特别地，本发明确定特定扫描周期的护理位。生成伪随机模式，然后将其与特定的扫描周期对准。如果伪随机模式包含护理位，具有正确的值并且在模式内的适当位置，则该对准测试一个或多个逻辑器件。

2. 发明授权

US5691990A Hybrid partial scan method 失效
标题翻译：混合部分扫描法
公开(公告)号：US5691990A
公开(公告)日：1997-11-25
申请号：US759286
申请日：1996-12-02
申请人： Rohit Kapur , Thomas J. Snethen , Kamran K. Zarrineh
发明人： Rohit Kapur , Thomas J. Snethen , Kamran K. Zarrineh
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318586
摘要： An efficient method of selecting flip-flops to be made scannable in a digital integrated circuit design for purposes of improving testability without incurring the overhead of full-scan, comprising the steps of (a) partitioning the faults in the circuit into a first fault type and a second fault type, (b) selecting a static characterization algorithm for characterizing the first and second fault types, (c) determining the relationship between attainable fault coverage and the characterized values for the first and second fault types, (d) characterizing the first and second fault types for each candidate flip-flop for scan in the digital integrated circuit with the static characterization algorithm, (e) determining the first and second fault types that are the closest together in value, (f) selecting the flip-flop associated with the first and second fault types determined in step (e), (g) forming a shift register with flip-flop selected in step (f), (h) repeating steps (d)-(g) until the attainable fault coverage determined in step (c) is attained, and (i) generating test data for the network with the shift register configured in step (h).
摘要翻译：为了提高可测试性而不引起全扫描的开销，选择在数字集成电路设计中可扫描的触发器的有效方法包括以下步骤：（a）将电路中的故障划分为第一故障类型和第二故障类型，（b）选择表征第一和第二故障类型的静态表征算法，（c）确定可达到的故障覆盖与第一和第二故障类型的特征值之间的关系，（d）使用静态表征算法在数字集成电路中扫描每个候选触发器的第一和第二故障类型，（e）确定在值中最接近的第一和第二故障类型，（f）选择触发器与在步骤（e）中确定的第一和第二故障类型相关联，（g）在步骤（f）中形成具有触发器的移位寄存器，（h）重复步骤（d） - （g）获得在步骤（c）中确定的可达到的故障覆盖范围，并且（i）利用在步骤（h）中配置的移位寄存器生成网络的测试数据。

3. 发明授权

US3961250A Logic network test system with simulator oriented fault test generator 失效
公开(公告)号：US3961250A
公开(公告)日：1976-06-01
申请号：US468108
申请日：1974-05-08
申请人： Thomas J. Snethen
发明人： Thomas J. Snethen
IPC分类号： G01R31/28 , G01R31/3183 , G06F11/22 , G01R15/12 , G06F11/00
CPC分类号： G01R31/318392 , G01R31/318371
摘要： Disclosed is a technique for testing highly complex, functional logic where long sequences of test patterns are needed. A logic network to be tested comprises a large number of logic blocks. The inputs to several of these logic blocks are also the primary inputs (PI) to the logic network to be tested while the output of several of the logic blocks are also outputs (PO) of the logic network to be tested. However, the inputs and outputs of many logic blocks of the network to be tested are inaccessible since as is well known in large scale integration (LSI), a large number of internal circuit nodes cannot be probed directly. In accordance with the present disclosure, such a logic network to be tested is simulated and each of the logic blocks as well as the inputs and outputs of each of these logic blocks is uniquely defined. A first test pattern is then applied to the primary inputs (PI) of the network to set the logic levels on these primary inputs to known values. A particular one of the logic blocks within the network is then selected and a specific fault associated with the particular logic block is assumed. A test value for this assumed specific fault in the simulated network is then propagated towards a primary output, one logic stage at a time, by backtracing through the network to a primary input to determine which primary input value must be altered in order to propagate the assumed fault towards a primary output. Without developing an entire test sequence, analysis at each step determines whether the test is in fact progressing by propagating the test value through the network toward the primary input. The term "test value" is defined as the binary vaue of a point within the logic network that is opposite from that expected in the absence of the assumed fault. When a "test value" has been successfully propagated to a primary output (PO), then it is known that the particular sequence of input test patterns is suitable for detecting the specific fault assumed in the simulator. By applying the same sequence of test patterns to the actual network under test and comparing the primary outputs of the network under test and primary outputs of the simulated network, it is determined whether the particular assumed simulated fault is actually present in the network under test. On a real time basis, each time a successive pattern is applied to the simulated network, it is analyzed, and if found unsuitable, it is discarded and a different changed input pattern is sought by backtracing to a primary input through a different path. Each successive pattern is applied to the network under test only if found to be valid.

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