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1. 发明授权

US08252689B2 Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process 有权
标题翻译：化学机械平面化方法及其制造方法
公开(公告)号：US08252689B2
公开(公告)日：2012-08-28
申请号：US13142736
申请日：2011-04-12
申请人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
发明人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L21/31155 , H01L29/66545 , H01L29/66606 , H01L29/78
摘要： The present invention provides a chemical-mechanical planarization method. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP.
摘要翻译：本发明提供了一种化学机械平面化方法。化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率由CMP。

2. 发明申请

US20120135589A1 CHEMICAL-MECHANICAL PLANARIZATION METHOD AND METHOD FOR FABRICATING METAL GATE IN GATE-LAST PROCESS 有权
标题翻译：化学机械平面化方法和方法，用于在门过程中制造金属门
公开(公告)号：US20120135589A1
公开(公告)日：2012-05-31
申请号：US13142736
申请日：2011-04-12
申请人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
发明人： Tao Yang , Jinbiao Liu , Xiaobin He , Chao Zhao , Dapeng Chen
IPC分类号： H01L21/306 , H01L21/304 , H01L21/28
CPC分类号： H01L21/31053 , H01L21/31155 , H01L29/66545 , H01L29/66606 , H01L29/78
摘要： The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP, thereby improving the within-die uniformity of the process, consequently, there will not be excess metal in the insulating layer between gates, thereby preventing device short circuit risk induced by POP CMP process.
摘要翻译：本发明提供一种化学机械平面化方法及其制造方法。化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率通过CMP，从而提高了工艺的管芯内均匀性，因此在栅极之间的绝缘层中不会有过多的金属，从而防止POP CMP工艺引起的器件短路风险。

3. 发明申请

US20130059434A1 METHOD FOR MANUFACTURING ELECTRODES AND WIRES IN GATE LAST PROCESS 审中-公开
标题翻译：在门过程中制造电极和电线的方法
公开(公告)号：US20130059434A1
公开(公告)日：2013-03-07
申请号：US13509722
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Xiaobin He , Yihong Lu
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Xiaobin He , Yihong Lu
IPC分类号： H01L21/28
CPC分类号： H01L29/66606 , H01L21/28518 , H01L21/76802 , H01L21/7684 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process. Such a design has the advantages of simplifying complexity of process integration on one hand and greatly strengthening control of defects by CMP process on the other hand, thereby avoiding the defects like erosion and dishing that may be produced between different metal materials.
摘要翻译：本发明提供了一种用于在栅极最后工艺中同时制造栅电极和接触导线的方法，包括以下步骤：在衬底上的层间电介质层中形成栅极沟槽; 在栅极沟槽和层间电介质层上形成填充层; 蚀刻填充层和层间电介质层以暴露衬底，从而形成源极/漏极接触孔; 去除填充层以暴露栅极沟槽和源极/漏极接触孔; 在源极/漏极接触孔中形成金属硅化物; 在栅极沟槽中沉积栅极电介质层和金属栅极; 在栅极沟槽和源极/漏极接触孔中填充金属; 并平坦化填充的金属。根据本发明的制造方法，栅极电极线将由与接触孔相同的金属材料制成，使得两者可以通过一个CMP工艺制造。这样的设计一方面简化了工艺集成的复杂性，另一方面通过CMP工艺大大加强了缺陷的控制，从而避免了不同金属材料之间可能产生的侵蚀和凹陷等缺陷。

4. 发明授权

US08541296B2 Method of manufacturing dummy gates in gate last process 有权
标题翻译：门最后工序中制造虚拟门的方法
公开(公告)号：US08541296B2
公开(公告)日：2013-09-24
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

5. 发明授权

US08501500B2 Method for monitoring the removal of polysilicon pseudo gates 有权
标题翻译：监测多晶硅伪栅极去除的方法
公开(公告)号：US08501500B2
公开(公告)日：2013-08-06
申请号：US13499288
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/66545
摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
摘要翻译：本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈，准确地不会对晶片造成任何损坏。

6. 发明申请

US20130059435A1 Method of Manufacturing Dummy Gates in Gate Last Process 有权
标题翻译：闸门最后工序制造虚拟闸门的方法
公开(公告)号：US20130059435A1
公开(公告)日：2013-03-07
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

7. 发明申请

US20120322172A1 METHOD FOR MONITORING THE REMOVAL OF POLYSILICON PSEUDO GATES 有权
标题翻译：用于监测多晶硅PSEUDO门的拆卸方法
公开(公告)号：US20120322172A1
公开(公告)日：2012-12-20
申请号：US13499288
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/66545
摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
摘要翻译：本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈，准确地不会对晶片造成任何损坏。

8. 发明授权

US08946071B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08946071B2
公开(公告)日：2015-02-03
申请号：US14364950
申请日：2012-03-23
申请人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
发明人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/84 , H01L29/417 , H01L29/45
CPC分类号： H01L21/823814 , H01L21/2255 , H01L21/28518 , H01L21/823418 , H01L21/823443 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/41725 , H01L29/45 , H01L29/456 , H01L29/665
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved.
摘要翻译：本发明公开了一种半导体器件的制造方法，包括：在基板上形成栅叠层结构; 在栅极层叠结构的两侧形成源极/漏极区域和栅极侧壁间隔物; 至少在源/漏区中沉积镍基金属层; 进行第一退火，使得源极/漏极区中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使富Ni相的金属硅化物转变为镍系金属硅化物，同时在镍基金属硅化物与源极/漏极区之间的界面处形成掺杂离子的偏析区域。根据本发明的方法在将掺杂离子注入到金属硅化物的富Ni相中之后执行退火，从而提高掺杂离子的固溶度并形成高度浓缩的掺杂离子的偏析区，因此SBH 镍基金属二氧化硅和源极/漏极区域之间的金属 - 半导体接触被有效地降低，接触电阻降低，并且器件的驱动能力得到改善。

9. 发明授权

US08802518B2 Semiconducor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08802518B2
公开(公告)日：2014-08-12
申请号：US13395608
申请日：2011-10-17
申请人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L21/8234 , H01L29/51 , H01L29/423
CPC分类号： H01L21/82345 , H01L21/28114 , H01L21/823468 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.
摘要翻译：一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

10. 发明申请

US20130241004A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130241004A1
公开(公告)日：2013-09-19
申请号：US13520618
申请日：2012-04-11
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7845
摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且栅极填充层具有第二应力。形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是增强。

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