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1. 发明授权

US09419095B2 Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process 有权
标题翻译：最后一个进程中的伪栅极的制造方法和栅极最后工艺中的虚拟栅极的制造方法
公开(公告)号：US09419095B2
公开(公告)日：2016-08-16
申请号：US14119864
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L21/338 , H01L29/66 , H01L29/423 , H01L29/51 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/42364 , H01L29/513 , H01L29/518
摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.
摘要翻译：提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形硅。

2. 发明授权

US09136160B2 Solid hole array and method for forming the same 有权
标题翻译：固体孔阵列及其形成方法
公开(公告)号：US09136160B2
公开(公告)日：2015-09-15
申请号：US13697372
申请日：2012-07-31
申请人： Lijun Dong , Chao Zhao
发明人： Lijun Dong , Chao Zhao
IPC分类号： H01L23/498 , H01L21/768 , H01L23/14 , H01L21/48
CPC分类号： H01L21/76802 , H01L21/486 , H01L23/147 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A solid hole array and a method for forming the same are disclosed. The solid hold array may comprise: substrate with a via; a top hole array base formed on a top surface of the substrate and a bottom hole array base formed on a bottom surface of the substrate, wherein a front hole is located in the top hole array base at a place corresponding to the via; and top protection layer formed on a surface and sidewalls of the top hole array base and a bottom protection layer formed on a surface of the bottom hole array base, wherein a rear window is located in the bottom hole array base and the bottom protection layer at a place corresponding to the via.
摘要翻译：公开了一种固体孔阵列及其形成方法。固体保持阵列可以包括：具有通孔的基底; 形成在所述基板的上表面上的顶孔阵列基座和形成在所述基板的底面的底孔阵列基座，其中，在与所述通孔相对应的位置处，所述顶孔阵列基座中的前孔位于所述顶孔阵列基底中; 以及形成在顶孔阵列基底的表面和侧壁上的顶部保护层和形成在底部孔阵列基底的表面上的底部保护层，其中后部窗口位于底部孔阵列基底中，底部保护层位于底部保护层一个对应于通道的地方。

3. 发明授权

US09012965B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09012965B2
公开(公告)日：2015-04-21
申请号：US13379120
申请日：2011-04-22
申请人： Jun Luo , Chao Zhao
发明人： Jun Luo , Chao Zhao
IPC分类号： H01L29/76 , H01L29/47 , H01L29/66 , H01L29/78 , H01L21/285 , H01L21/265
CPC分类号： H01L29/47 , H01L21/26506 , H01L21/28518 , H01L29/66545 , H01L29/66643 , H01L29/7839
摘要： The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.
摘要翻译：本发明公开了一种通过门最后工艺制造的新型MOSFET器件及其实现方法，该器件包括：衬底; 栅极叠层结构位于衬底的沟道区上，其任一侧消除了传统隔离间隔物; 构成源极/漏极区域的外延生长的超薄金属硅化物。其中该器件消除了传统隔离间隔物下面的高电阻区域; 在源极/漏极和沟道区之间形成具有经过离子注入的掺杂剂偏析区域，这降低了金属硅化物源极/漏极与沟道之间的肖特基势垒高度。同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

4. 发明授权

US08994119B2 Semiconductor device with gate stacks having stress and method of manufacturing the same 有权
标题翻译：具有应力的栅极堆叠的半导体器件及其制造方法
公开(公告)号：US08994119B2
公开(公告)日：2015-03-31
申请号：US13520618
申请日：2012-04-11
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L29/51 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7845
摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且栅极填充层具有第二应力。形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也增强。

5. 发明申请

US20140302644A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140302644A1
公开(公告)日：2014-10-09
申请号：US14361944
申请日：2012-03-23
申请人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
发明人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
IPC分类号： H01L21/28 , H01L21/283 , H01L29/66
CPC分类号： H01L21/28097 , H01L21/283 , H01L29/66477 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7833
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.
摘要翻译：本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域，因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

6. 发明授权

US08816326B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08816326B2
公开(公告)日：2014-08-26
申请号：US13497249
申请日：2011-11-25
申请人： Huaxiang Yin , Jun Luo , Chao Zhao , Honggang Liu , Dapeng Chen
发明人： Huaxiang Yin , Jun Luo , Chao Zhao , Honggang Liu , Dapeng Chen
IPC分类号： H01L29/78 , H01L29/66 , H01L29/778 , H01L29/08
CPC分类号： H01L29/66462 , H01L29/0895 , H01L29/7391 , H01L29/7785 , Y10S977/938
摘要： A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.
摘要翻译：一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。

7. 发明授权

US08686534B2 Trench isolation structure and method for forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US08686534B2
公开(公告)日：2014-04-01
申请号：US13145301
申请日：2011-04-22
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232 , H01L29/02
摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
摘要翻译：提供了沟槽隔离结构及其形成方法。沟槽隔离结构包括：半导体衬底和形成在半导体衬底中并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

8. 发明授权

US08647987B2 Method for improving uniformity of chemical-mechanical planarization process 有权
标题翻译：改善化学机械平面化工艺均匀性的方法
公开(公告)号：US08647987B2
公开(公告)日：2014-02-11
申请号：US13698283
申请日：2012-06-12
申请人： Tao Yang , Chao Zhao , Junfeng Li
发明人： Tao Yang , Chao Zhao , Junfeng Li
IPC分类号： H01L21/302 , H01L21/461 , H01L21/311
CPC分类号： H01L21/30625 , H01L21/31053 , H01L21/31056 , H01L22/26 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.
摘要翻译：本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二绝缘隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。根据本发明的化学机械平面化工艺的均匀性提高方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

9. 发明申请

US20140001646A1 SOLID HOLE ARRAY AND MANUFACTURE METHOD THEREOF 有权
标题翻译：固体盖阵列及其制造方法
公开(公告)号：US20140001646A1
公开(公告)日：2014-01-02
申请号：US13697372
申请日：2012-07-31
申请人： Lijun Dong , Chao Zhao
发明人： Lijun Dong , Chao Zhao
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/76802 , H01L21/486 , H01L23/147 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A solid hole array and a manufacture method thereof are provided. The method for manufacturing the solid hole array comprises: forming a top hole array base and a bottom hole array base on a top surface and a bottom surface of a substrate respectively; forming a front hole in the top hole array base; forming a top protection layer on the substrate with the top hole array base, and forming a bottom protection layer on the bottom hole array base; forming a rear window in the bottom hole array base and the bottom protection layer; and etching through the substrate by alkali corrosion to connect the front hole with the rear window. In addition, the present disclosure also provides a solid hole array. Using the method of the present disclosure, the intensity of the front film is enhanced, the process steps are simplified, the cost is decreased, and a large scale manufacture is more likely.
摘要翻译：提供了一种固体孔阵列及其制造方法。固体孔阵列的制造方法包括：分别在衬底的顶表面和底表面上形成顶孔阵列基底和底孔阵列基底; 在顶孔阵列基底中形成前孔; 在顶孔阵列基底上形成顶层保护层，在底孔阵列基底上形成底层保护层; 在底孔阵列基底和底部保护层中形成后窗; 并通过碱腐蚀蚀刻基板，将前孔与后窗连接起来。此外，本公开还提供了一种固体孔阵列。利用本公开的方法，提高了前膜的强度，简化了工艺步骤，降低了成本，并且更有可能进行大规模制造。

10. 发明授权

US08557677B2 Stack-type semiconductor device and method for manufacturing the same 有权
标题翻译：叠层型半导体器件及其制造方法
公开(公告)号：US08557677B2
公开(公告)日：2013-10-15
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

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