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1. 发明授权

US08834155B2 Wafer transfer apparatus and wafer transfer method 有权
标题翻译：晶圆转印装置和晶片转印方法
公开(公告)号：US08834155B2
公开(公告)日：2014-09-16
申请号：US13140471
申请日：2011-04-11
申请人： Chunlong Li , Junfeng Li
发明人： Chunlong Li , Junfeng Li
IPC分类号： F27D15/02 , H01L21/677 , H01L21/67
CPC分类号： H01L21/67766 , H01L21/67109 , H01L21/67778
摘要： A water transfer apparatus and a wafer transfer method are provided. The wafer transfer apparatus is provided with a heating component and a cooling component, the heating component heats the wafer carrying component to a temperature the same as the wafer when it is just unloaded from the rapid thermal anneal tool, and the cooling component cools the wafer carrying component along with the wafer to room temperature, thereby avoiding the large temperature difference between the wafer and the wafer transfer apparatus, preventing the high thermal stress induced inside the wafer during wafer transfer, avoiding wafer breakage, and ensuring the completeness of the wafer.
摘要翻译：提供了一种输水装置和晶片转印方法。晶片传送装置设置有加热部件和冷却部件，当刚刚从快速热退火工具卸载时，加热部件将晶片承载部件加热到与晶片相同的温度，并且冷却部件冷却晶片携带部件与晶片一起至室温，从而避免晶片和晶片传送装置之间的温差大，防止晶片转印期间在晶片内引起的高热应力，避免晶片断裂，并确保晶片的完整性。

2. 发明申请

US20140227878A1 Method for Manufacturing Small-Size Fin-Shaped Structure 审中-公开
标题翻译：制造小尺寸鳍形结构的方法
公开(公告)号：US20140227878A1
公开(公告)日：2014-08-14
申请号：US14342421
申请日：2012-03-05
申请人： Tao Yang , Chao Zhao , Junfeng Li , Yihong Lu
发明人： Tao Yang , Chao Zhao , Junfeng Li , Yihong Lu
IPC分类号： H01L21/308
CPC分类号： H01L21/3086 , H01L21/28123 , H01L21/31111 , H01L29/66795 , H01L29/785
摘要： A method for manufacturing a small-size fin-shaped structure, comprising: forming a first mask layer and a second mask layer on a substrate in sequence; etching the first mask layer and the second mask layer to form a hard mask pattern, wherein a second mask layer pattern is wider than a first mask layer pattern; eliminating the second mask layer pattern; and performing a dry etching of the substrate by taking the first mask layer pattern as a mask, so as to form a fin-shaped structure. According to the method for manufacturing a small-size fin-shaped structure of the present invention, firstly a large-size hard mask is prepared, then a width controllable small-size hard mask is prepared through a wet corrosion, and finally the bulk silicon wafer is etched, so as to obtain the required small-size fin-shaped structure, thereby improving the electrical properties and the integration level of the device, simplifying the processes and reducing the cost.
摘要翻译：一种制造小尺寸鳍状结构的方法，包括：依次在基板上形成第一掩模层和第二掩模层; 蚀刻第一掩模层和第二掩模层以形成硬掩模图案，其中第二掩模层图案比第一掩模层图案宽; 消除第二掩模层图案; 并且通过以第一掩模层图案作为掩模来进行基板的干蚀刻，以便形成鳍状结构。根据本发明的小型翅片状结构体的制造方法，首先制作大尺寸的硬掩模，然后通过湿式腐蚀制备宽度可控的小尺寸硬掩模，最后制成体硅晶片被蚀刻，从而获得所需的小尺寸鳍状结构，从而提高了器件的电气特性和集成度，简化了工艺并降低了成本。

3. 发明授权

US08541296B2 Method of manufacturing dummy gates in gate last process 有权
标题翻译：门最后工序中制造虚拟门的方法
公开(公告)号：US08541296B2
公开(公告)日：2013-09-24
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

4. 发明授权

US08501500B2 Method for monitoring the removal of polysilicon pseudo gates 有权
标题翻译：监测多晶硅伪栅极去除的方法
公开(公告)号：US08501500B2
公开(公告)日：2013-08-06
申请号：US13499288
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/66545
摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
摘要翻译：本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈，准确地不会对晶片造成任何损坏。

5. 发明申请

US20120247723A1 WAFER TRANSFER APPARATUS AND WAFER TRANSFER METHOD 有权
标题翻译： WAFER传输设备和传输方法
公开(公告)号：US20120247723A1
公开(公告)日：2012-10-04
申请号：US13140471
申请日：2011-04-11
申请人： Chunlong Li , Junfeng Li
发明人： Chunlong Li , Junfeng Li
IPC分类号： B25J11/00 , F25B29/00
CPC分类号： H01L21/67766 , H01L21/67109 , H01L21/67778
摘要： A water transfer apparatus and a wafer transfer method are provided. The wafer transfer apparatus is provided with a heating component and a cooling component, the heating component heats the wafer carrying component to a temperature the same as the wafer when it is just unloaded from the rapid thermal anneal tool, and the cooling component cools the wafer carrying component along with the wafer to room temperature, thereby avoiding the large temperature difference between the wafer and the wafer transfer apparatus, preventing the high thermal stress induced inside the wafer during wafer transfer, avoiding wafer breakage, and ensuring the completeness of the wafer.
摘要翻译：提供了一种输水装置和晶片转印方法。晶片传送装置设置有加热部件和冷却部件，当刚刚从快速热退火工具卸载时，加热部件将晶片承载部件加热到与晶片相同的温度，并且冷却部件冷却晶片携带部件与晶片一起至室温，从而避免晶片和晶片传送装置之间的温差大，防止晶片转印期间在晶片内引起的高热应力，避免晶片断裂，并确保晶片的完整性。

6. 发明授权

US09419095B2 Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process 有权
标题翻译：最后一个进程中的伪栅极的制造方法和栅极最后工艺中的虚拟栅极的制造方法
公开(公告)号：US09419095B2
公开(公告)日：2016-08-16
申请号：US14119864
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L21/338 , H01L29/66 , H01L29/423 , H01L29/51 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/42364 , H01L29/513 , H01L29/518
摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.
摘要翻译：提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形硅。

7. 发明申请

US20140302644A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140302644A1
公开(公告)日：2014-10-09
申请号：US14361944
申请日：2012-03-23
申请人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
发明人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
IPC分类号： H01L21/28 , H01L21/283 , H01L29/66
CPC分类号： H01L21/28097 , H01L21/283 , H01L29/66477 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7833
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.
摘要翻译：本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域，因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

8. 发明授权

US08647987B2 Method for improving uniformity of chemical-mechanical planarization process 有权
标题翻译：改善化学机械平面化工艺均匀性的方法
公开(公告)号：US08647987B2
公开(公告)日：2014-02-11
申请号：US13698283
申请日：2012-06-12
申请人： Tao Yang , Chao Zhao , Junfeng Li
发明人： Tao Yang , Chao Zhao , Junfeng Li
IPC分类号： H01L21/302 , H01L21/461 , H01L21/311
CPC分类号： H01L21/30625 , H01L21/31053 , H01L21/31056 , H01L22/26 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.
摘要翻译：本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二绝缘隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。根据本发明的化学机械平面化工艺的均匀性提高方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

9. 发明申请

US20120322172A1 METHOD FOR MONITORING THE REMOVAL OF POLYSILICON PSEUDO GATES 有权
标题翻译：用于监测多晶硅PSEUDO门的拆卸方法
公开(公告)号：US20120322172A1
公开(公告)日：2012-12-20
申请号：US13499288
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/66545
摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
摘要翻译：本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈，准确地不会对晶片造成任何损坏。

10. 发明申请

US20120252225A1 SEMICONDUCTOR FABRICATION METHOD 审中-公开
标题翻译：半导体制造方法
公开(公告)号：US20120252225A1
公开(公告)日：2012-10-04
申请号：US13140549
申请日：2011-04-11
申请人： Chunlong Li , Junfeng Li
发明人： Chunlong Li , Junfeng Li
IPC分类号： H01L21/316 , B82Y40/00
CPC分类号： H01L21/02238
摘要： A semiconductor fabrication method is provided, in which a protective layer is deposited on the dummy wafer such that the protective layer fully encases the dummy wafer. Therefore, the dummy wafer will not be oxidized during thermal oxidation, thereby reducing dummy wafer consumption, decreasing production cost, avoiding particulate matter produced due to oxidation of the dummy wafer, and preventing the wafer to be oxidized from contamination.
摘要翻译：提供一种半导体制造方法，其中保护层沉积在伪晶片上，使得保护层完全包住虚设晶片。因此，在热氧化期间，伪晶片不会被氧化，从而减少了虚设晶片消耗，降低了生产成本，避免了由于虚设晶片的氧化而产生的颗粒物质，并且防止晶片被污染而被氧化。

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