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1. 发明申请

US20130059434A1 METHOD FOR MANUFACTURING ELECTRODES AND WIRES IN GATE LAST PROCESS 审中-公开
标题翻译：在门过程中制造电极和电线的方法
公开(公告)号：US20130059434A1
公开(公告)日：2013-03-07
申请号：US13509722
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Xiaobin He , Yihong Lu
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Xiaobin He , Yihong Lu
IPC分类号： H01L21/28
CPC分类号： H01L29/66606 , H01L21/28518 , H01L21/76802 , H01L21/7684 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process. Such a design has the advantages of simplifying complexity of process integration on one hand and greatly strengthening control of defects by CMP process on the other hand, thereby avoiding the defects like erosion and dishing that may be produced between different metal materials.
摘要翻译：本发明提供了一种用于在栅极最后工艺中同时制造栅电极和接触导线的方法，包括以下步骤：在衬底上的层间电介质层中形成栅极沟槽; 在栅极沟槽和层间电介质层上形成填充层; 蚀刻填充层和层间电介质层以暴露衬底，从而形成源极/漏极接触孔; 去除填充层以暴露栅极沟槽和源极/漏极接触孔; 在源极/漏极接触孔中形成金属硅化物; 在栅极沟槽中沉积栅极电介质层和金属栅极; 在栅极沟槽和源极/漏极接触孔中填充金属; 并平坦化填充的金属。根据本发明的制造方法，栅极电极线将由与接触孔相同的金属材料制成，使得两者可以通过一个CMP工艺制造。这样的设计一方面简化了工艺集成的复杂性，另一方面通过CMP工艺大大加强了缺陷的控制，从而避免了不同金属材料之间可能产生的侵蚀和凹陷等缺陷。

2. 发明申请

US20130059435A1 Method of Manufacturing Dummy Gates in Gate Last Process 有权
标题翻译：闸门最后工序制造虚拟闸门的方法
公开(公告)号：US20130059435A1
公开(公告)日：2013-03-07
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

3. 发明授权

US08541296B2 Method of manufacturing dummy gates in gate last process 有权
标题翻译：门最后工序中制造虚拟门的方法
公开(公告)号：US08541296B2
公开(公告)日：2013-09-24
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

4. 发明申请

US20140227878A1 Method for Manufacturing Small-Size Fin-Shaped Structure 审中-公开
标题翻译：制造小尺寸鳍形结构的方法
公开(公告)号：US20140227878A1
公开(公告)日：2014-08-14
申请号：US14342421
申请日：2012-03-05
申请人： Tao Yang , Chao Zhao , Junfeng Li , Yihong Lu
发明人： Tao Yang , Chao Zhao , Junfeng Li , Yihong Lu
IPC分类号： H01L21/308
CPC分类号： H01L21/3086 , H01L21/28123 , H01L21/31111 , H01L29/66795 , H01L29/785
摘要： A method for manufacturing a small-size fin-shaped structure, comprising: forming a first mask layer and a second mask layer on a substrate in sequence; etching the first mask layer and the second mask layer to form a hard mask pattern, wherein a second mask layer pattern is wider than a first mask layer pattern; eliminating the second mask layer pattern; and performing a dry etching of the substrate by taking the first mask layer pattern as a mask, so as to form a fin-shaped structure. According to the method for manufacturing a small-size fin-shaped structure of the present invention, firstly a large-size hard mask is prepared, then a width controllable small-size hard mask is prepared through a wet corrosion, and finally the bulk silicon wafer is etched, so as to obtain the required small-size fin-shaped structure, thereby improving the electrical properties and the integration level of the device, simplifying the processes and reducing the cost.
摘要翻译：一种制造小尺寸鳍状结构的方法，包括：依次在基板上形成第一掩模层和第二掩模层; 蚀刻第一掩模层和第二掩模层以形成硬掩模图案，其中第二掩模层图案比第一掩模层图案宽; 消除第二掩模层图案; 并且通过以第一掩模层图案作为掩模来进行基板的干蚀刻，以便形成鳍状结构。根据本发明的小型翅片状结构体的制造方法，首先制作大尺寸的硬掩模，然后通过湿式腐蚀制备宽度可控的小尺寸硬掩模，最后制成体硅晶片被蚀刻，从而获得所需的小尺寸鳍状结构，从而提高了器件的电气特性和集成度，简化了工艺并降低了成本。

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