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1. 发明授权

US5270226A Manufacturing method for LDDFETS using oblique ion implantion technique 失效
标题翻译：使用斜离子注入技术的LDDFETS的制造方法
公开(公告)号：US5270226A
公开(公告)日：1993-12-14
申请号：US332714
申请日：1989-04-03
申请人： Takashi Hori , Toshiki Yabu , Kazumi Kurimoto , Genshu Fuse
发明人： Takashi Hori , Toshiki Yabu , Kazumi Kurimoto , Genshu Fuse
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7836
摘要： By symmetrically forming source and drain regions to the gate electrodes, electrically symmetrical transistor characteristics are obtained. After forming the first source and drain regions by large-tilt-angle ion implantation, without a sidewall in the gate electrode or after forming a sidewall shorter than the distance in the lateral direction of the second source and drain regions from the end of the mask for ion implantation, the diffusion of the second source and drain regions in the lateral direction is restricted to the maximum extent by heat treatment for a short time, and then the end of the gate electrode and the end of the second source and drain regions are matched, or their overlap region is formed. As a result, the manufacturing method of the MOS transistor results in both high performance and high reliability.
摘要翻译：通过对栅极对称地形成源极和漏极区域，获得电对称的晶体管特性。在通过大倾斜角度离子注入形成第一源极和漏极区域之后，在栅电极中没有侧壁或在形成比第二源极和漏极区域的横向方向上距离掩模的端部短的侧壁对于离子注入，第二源极和漏极区域在横向上的扩散通过短时间的热处理被限制在最大程度，然后栅电极的端部和第二源极和漏极区域的端部是匹配，或者形成它们的重叠区域。结果，MOS晶体管的制造方法具有高性能和高可靠性。

2. 发明授权

US5451799A MOS transistor for protection against electrostatic discharge 失效
标题翻译：用于防止静电放电的MOS晶体管
公开(公告)号：US5451799A
公开(公告)日：1995-09-19
申请号：US173631
申请日：1993-12-22
申请人： Kazumi Kurimoto , Isao Miyanaga , Atsushi Hori
发明人： Kazumi Kurimoto , Isao Miyanaga , Atsushi Hori
IPC分类号： H01L27/02 , H01L29/10 , H01L29/417 , H01L29/739 , H01L29/68
CPC分类号： H01L29/41758 , H01L27/0266 , H01L29/1087 , H01L29/41725 , H01L29/7393 , Y10S257/906
摘要： A MOS transistor for protection against electrostatic discharge includes a semiconductor substrate; an island including a source region and a drain region provided in the semiconductor substrate; an isolation region provided in the semiconductor substrate so as to surround the island; a gate insulating layer provided on the semiconductor substrate; a gate electrode provided on the gate insulating layer; and a distributing device for distributing an electric current generated by an electrostatic voltage applied to the drain region into the drain region.
摘要翻译：用于防止静电放电的MOS晶体管包括半导体衬底; 包括设置在所述半导体衬底中的源区和漏区的岛; 设置在所述半导体衬底中以围绕所述岛的隔离区; 设置在所述半导体基板上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 以及分配装置，用于将由施加到所述漏极区域的静电电压产生的电流分配到所述漏极区域中。

3. 发明授权

US5306655A Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions 失效
标题翻译：具有轻掺杂漏极和源极扩散区域的MOS场效应晶体管的结构和制造方法
公开(公告)号：US5306655A
公开(公告)日：1994-04-26
申请号：US977462
申请日：1992-11-17
申请人： Kazumi Kurimoto
发明人： Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/28114 , H01L29/42368 , H01L29/42376 , H01L29/6659 , H01L29/7836 , H01L21/26586
摘要： Structures and methods of manufacture are described for a MOS FET that is suitable for extreme miniaturization, of a type in which lightly doped drain and source diffusion regions are formed respectively adjoining the conventional highly doped drain and source diffusion regions in the semiconductor substrate surface, for reducing electric field concentration in the drain region. The underside of the gate electrode of the FET is formed with a downwardly protruding convex shape, so that a thick region of gate insulation film is positioned between the drain diffusion regions and the most closely adjacent part of the gate electrode, whereby gate-to-drain stray capacitance and the vertical component of electric field within the lightly doped drain diffusion region are reduced. The underside of the gate electrode can be formed in the required shape by various methods which effectively utilize self alignment and are easily adapted to currently used types of LSI manufacturing process.
摘要翻译：对于适用于极小型化的MOS FET描述了制造的结构和方法，其中形成了轻掺杂漏极和源极扩散区，分别与半导体衬底表面中常规的高掺杂漏极和源极扩散区相邻，降低漏极区域中的电场浓度。 FET的栅电极的下侧形成有向下突出的凸出形状，使得栅极绝缘膜的厚区域位于漏极扩散区域和栅极电极的最接近的部分之间，由此栅极 - 漏极杂散电容和轻掺杂漏极扩散区域内的电场的垂直分量减小。栅电极的下侧可以通过各种有效利用自对准的方法形成所需的形状，并且容易适应于当前使用的LSI制造工艺。

4. 发明授权

US07271449B2 Semiconductor device having triple-well structure 有权
标题翻译：具有三重结构的半导体器件
公开(公告)号：US07271449B2
公开(公告)日：2007-09-18
申请号：US11119849
申请日：2005-05-03
申请人： Makoto Misaki , Kazumi Kurimoto
发明人： Makoto Misaki , Kazumi Kurimoto
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0928 , H01L21/823892
摘要： A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.
摘要翻译：半导体器件具有第一导电类型的半导体衬底，形成为从半导体衬底的表面向其内部延伸的第一导电类型的第一阱区，第二导电性的一对第二阱区，形成为从半导体衬底的表面朝向其内部延伸以将第一阱区域夹在其间的方式，以及形成在第一阱区域和第二阱区域中的第二阱区域的第三阱区域，半导体衬底中的一对第二阱区。第三阱区将一对第二阱区彼此电连接。第一阱区域的至少一部分连接到半导体衬底的不形成第三阱区域的区域。

5. 发明申请

US20060086990A1 Semiconductor device and fabrication method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060086990A1
公开(公告)日：2006-04-27
申请号：US11119849
申请日：2005-05-03
申请人： Makoto Misaki , Kazumi Kurimoto
发明人： Makoto Misaki , Kazumi Kurimoto
IPC分类号： H01L29/76
CPC分类号： H01L27/0928 , H01L21/823892
摘要： A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.
摘要翻译：半导体器件具有第一导电类型的半导体衬底，形成为从半导体衬底的表面向其内部延伸的第一导电类型的第一阱区，第二导电性的一对第二阱区，形成为从半导体衬底的表面朝向其内部延伸以将第一阱区域夹在其间的方式形成，并且形成在第一阱区域和第二阱区域中的第二导电类型的第三阱区域半导体衬底中的一对第二阱区。第三阱区将一对第二阱区彼此电连接。第一阱区域的至少一部分连接到半导体衬底的不形成第三阱区域的区域。

6. 发明授权

US5675168A Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device 失效
标题翻译：具有偏离源极和漏极区域的栅极绝缘体区域的非对称MOS器件，以及包括这种MOS器件的ESD保护电路
公开(公告)号：US5675168A
公开(公告)日：1997-10-07
申请号：US415928
申请日：1995-04-03
申请人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
发明人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
IPC分类号： H01L27/02 , H01L27/088 , H01L29/08 , H01L29/78 , H01L23/60
CPC分类号： H01L27/0266 , H01L27/088 , H01L29/0847 , H01L29/7835 , H01L2924/0002
摘要： An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.
摘要翻译：公开了一种不对称MOS器件，其包括具有第一区域的表面的第一导电类型的半导体层和与第一区域偏移的第二区域; 位于所述半导体层表面的第一区域上的栅极绝缘体层; 位于栅极绝缘体层上的栅电极; 以及第二导电类型的源极区域和第二导电类型的漏极区域，每个位于该表面的第二区域下方的半导体层中。表面的第一区域和源区域的表面之间的区域的电阻小于表面的第一区域和漏极区域的表面之间的区域的电阻。

7. 发明授权

US5405787A Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions 失效
标题翻译：具有轻掺杂漏极和源极扩散区域的MOS场效应晶体管的结构和制造方法
公开(公告)号：US5405787A
公开(公告)日：1995-04-11
申请号：US135649
申请日：1993-10-14
申请人： Kazumi Kurimoto
发明人： Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78 , H01L21/00
CPC分类号： H01L29/66583 , H01L21/28114 , H01L29/42368 , H01L29/42376 , H01L29/6659 , H01L29/7836 , H01L21/26586
摘要： Structures and methods of manufacture are described for a MOS FET that is suitable for extreme miniaturization, of a type in which lightly doped drain and source diffusion regions are formed respectively adjoining the conventional highly doped drain and source diffusion regions in the semiconductor substrate surface, for reducing electric field concentration in the drain region. The underside of the gate electrode of the FET is formed with a downwardly protruding convex shape, so that a thick region of gate insulation film is positioned between the drain diffusion regions and the most closely adjacent part of the gate electrode, whereby gate-to-drain stray capacitance and the vertical component of electric field within the lightly doped drain diffusion region are reduced. The underside of the gate electrode can be formed in the required shape by various methods which effectively utilize self alignment and are easily adapted to currently used types of LSI manufacturing process.
摘要翻译：对于适用于极小型化的MOS FET描述了制造的结构和方法，其中形成了轻掺杂漏极和源极扩散区，分别与半导体衬底表面中常规的高掺杂漏极和源极扩散区相邻，降低漏极区域中的电场浓度。 FET的栅电极的下侧形成有向下突出的凸出形状，使得栅极绝缘膜的厚区域位于漏极扩散区域和栅极电极的最接近的部分之间，由此栅极 - 漏极杂散电容和轻掺杂漏极扩散区域内的电场的垂直分量减小。栅电极的下侧可以通过各种有效利用自对准的方法形成所需的形状，并且容易适应于当前使用的LSI制造工艺。

8. 发明授权

US5386133A LDD FET with polysilicon sidewalls 失效
标题翻译： LDD FET具有多晶硅侧壁
公开(公告)号：US5386133A
公开(公告)日：1995-01-31
申请号：US225098
申请日：1994-04-08
申请人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
发明人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/66545 , Y10S257/90
摘要： An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished. Also, by forming the second conductivity type diffusion layer 7A on the sides of the gate electrode 5 through the medium of the thin insulating film 6 to be above the low concentration diffusion layer 3 and further contacting the low concentration diffusion layer 3, the high electrical field within the low concentration diffusion layer 3 is sufficiently ameliorated, generation of hot carriers is suppressed, and resistance to degradation is improved. Moreover, by controlling the high resistance second conductivity typetype diffusion layer 7 A at the sides of the gate electrode 5, the source resistance is decreased and driving capabilities are improved. At the same time the contact region of the source-drain electrode is miniaturized.
摘要翻译：本发明的目的是提供一种能够抑制热载流子劣化，提高驱动能力并且还使得能够使亚微米区域小型化的MOS半导体器件; 及其制造方法。通过在第二导电型低浓度扩散层3之间的第一导电型半导体衬底1的一个主表面上的栅极氧化膜4的介质形成栅电极5，使有效沟道长度大致等于栅极长度，实现了对亚微米区域的小型化和小型化。此外，通过在栅电极5的侧面上形成第二导电型扩散层7A，通过薄绝缘膜6的介质在低浓度扩散层3的上方进一步与低浓度扩散层3接触，充分改善了低浓度扩散层3内的场，抑制了热载流子的产生，提高了耐劣化性。此外，通过控制栅电极5侧的高电阻第二导电类型扩散层7A，源电阻降低，驱动能力提高。同时源极 - 漏极电极的接触区域被小型化。

9. 发明授权

US5808347A MIS transistor with gate sidewall insulating layer 失效
标题翻译：具有栅极侧壁绝缘层的MIS晶体管
公开(公告)号：US5808347A
公开(公告)日：1998-09-15
申请号：US23122
申请日：1993-02-26
申请人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
发明人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/336 , H01L29/76 , H01L27/088 , H01L29/94
CPC分类号： H01L29/6659 , H01L29/6656 , Y10S257/90
摘要： A MIS transistor has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.
摘要翻译： MIS晶体管具有第一导电类型的半导体衬底; 选择性地形成在半导体衬底上的栅极绝缘膜和栅电极; 绝缘膜，形成在所述栅电极的侧表面和所述半导体衬底上; 所述第一栅极侧壁层设置在所述绝缘膜的上表面和侧表面上并且具有大于所述绝缘膜的介电常数的介电常数，所述第一栅极侧壁层的高度小于所述栅电极的高度; 以及由覆盖所述第一栅极侧壁层的绝缘膜构成的第二栅极侧壁层。该MIS晶体管可以通过采用自对准的已知LSI生产技术制造，而不增加该工艺步骤的数量。

10. 发明授权

US5518944A MOS transistor and its fabricating method 失效
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US5518944A
公开(公告)日：1996-05-21
申请号：US308756
申请日：1994-09-19
申请人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
发明人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/66545 , Y10S257/90
摘要： An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished. Also, by forming the second conductivity type diffusion layer 7A on the sides of the gate electrode 5 through the medium of the thin insulating film 6 to be above the low concentration diffusion layer 3 and further contacting the low concentration diffusion layer 3, the high electrical field within the low concentration diffusion layer 3 is sufficiently ameliorated, generation of hot carriers is suppressed, and resistance to degradation is improved. Moreover, by controlling the high resistance second conductivity typetype diffusion layer 7 A at the sides of the gate electrode 5, the source resistance is decreased and driving capabilities are improved. At the same time the contact region of the source-drain electrode is miniaturized.
摘要翻译：本发明的目的是提供一种能够抑制热载流子劣化，提高驱动能力并且还使得能够使亚微米区域小型化的MOS半导体器件; 及其制造方法。通过在第二导电型低浓度扩散层3之间的第一导电型半导体衬底1的一个主表面上的栅极氧化膜4的介质形成栅电极5，使有效沟道长度大致等于栅极长度，实现了对亚微米区域的小型化和小型化。此外，通过在栅电极5的侧面上形成第二导电型扩散层7A，通过薄绝缘膜6的介质在低浓度扩散层3的上方进一步接触低浓度扩散层3，充分改善了低浓度扩散层3内的场，抑制了热载流子的产生，提高了耐劣化性。此外，通过控制栅电极5侧的高电阻第二导电类型扩散层7A，源电阻降低，驱动能力提高。同时源极 - 漏极电极的接触区域被小型化。

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