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1. 发明授权

US08857583B2 Hydraulic shock absorber 有权
标题翻译：液压减震器
公开(公告)号：US08857583B2
公开(公告)日：2014-10-14
申请号：US13521631
申请日：2010-12-01
申请人： Eiko Miyasato , Akira Hiroki , Junya Kaneko , Youji Takakuwa , Kengo Monden , Masayuki Ishikawa , Mariko Kessoku
发明人： Eiko Miyasato , Akira Hiroki , Junya Kaneko , Youji Takakuwa , Kengo Monden , Masayuki Ishikawa , Mariko Kessoku
IPC分类号： F16F9/10 , F16F9/36
CPC分类号： F16F9/363
摘要： A hydraulic shock absorber that can reduce outflow amount of oil by maximally removing an oil film attached to an outer periphery of a rod and that can achieve securement of high slidability between the rod and a rod packing and prevention of wear of the rod packing. A rod packing interposed between an outer periphery of a rod and an inner periphery of a rod-side end wall includes a first lip for scrapping off an oil film attached to the outer periphery of the rod, and a ring-shaped grease holding member for supplying holding grease to the outer periphery of the rod. The grease holding member is in contact with the outer periphery of the rod at a position closer to a rod distal end than the first lip.
摘要翻译：的液压缓冲器，可以通过最大限度地去除附着至一杆的外周上的油膜和能够实现杆和杆密封件的磨损而杆密封件和预防之间的高滑动性的固定减少油流出量。插入在杆的外周和杆侧端壁的内周之间的杆状填料包括用于废除附着在杆的外周的油膜的第一唇缘和用于向杆的外周供给保持油脂。润滑脂保持构件在比第一唇缘更靠近杆远端的位置处与杆的外周接触。

2. 发明授权

US06355963B1 MOS type semiconductor device having an impurity diffusion layer 有权
标题翻译：具有杂质扩散层的MOS型半导体器件
公开(公告)号：US06355963B1
公开(公告)日：2002-03-12
申请号：US09514924
申请日：2000-02-28
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H02L2994
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/66575 , H01L29/66659
摘要： A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate (1) under a source diffusion layer (2) is lower than the impurity concentration on a source side of a p-type impurity diffusion layer (6). Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage. Consequently, according to the present invention, a semiconductor device which can be operated at a low power consumption is realized.
摘要翻译：本发明的半导体器件形成为使得源极扩散层（2）下方的半导体衬底（1）的杂质浓度低于p型杂质扩散层（6）的源极侧的杂质浓度。因此，在本发明的半导体器件中，与传统的LDC结构相比，源极和衬底之间的p-n结的结电容较小。通常，器件的速度与通过将负载电容和器件的当前值的反相相乘得到的乘积成比例。因此，在将本发明应用于其中向源极和基板之间的区域施加电压的NAND型CMOS电路的电路的情况下，器件的速度不降低。另一方面，器件的功耗与通过将负载电容和施加电压的平方相乘获得的乘积成比例。因此，根据本发明，实现了能够以低功耗工作的半导体装置。

3. 发明授权

US6031268A Complementary semiconductor device and method for producing the same 失效
标题翻译：互补半导体器件及其制造方法
公开(公告)号：US6031268A
公开(公告)日：2000-02-29
申请号：US121350
申请日：1998-07-23
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10 , H01L29/76
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823807 , H01L27/0922 , H01L29/0847 , H01L29/1045
摘要： A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region. The asymmetric MOS transistor further includes an asymmetric impurity diffusion region having a nonuniform impurity concentration distribution in the channel region along a channel length direction such that an impurity concentration on a source side is set to be higher than an impurity concentration on a drain side, and an impurity concentration of a portion of the semiconductor substrate beneath the first source region is lower than the impurity concentration on the source side of the asymmetric impurity diffusion region.
摘要翻译：一种互补半导体器件，包括：具有主表面的半导体衬底，掺杂有第一导电类型的杂质的第一区域和掺杂有第二导电类型的杂质的第二区域; 设置在第二区域上的第一MOS晶体管; 以及设置在第一区域上的第二MOS晶体管。在这种互补半导体器件中，第一MOS晶体管和第二MOS晶体管中的至少一个是与作为第一区域或第二区域的对应区域的导电类型相同导电类型的非对称MOS晶体管。非对称MOS晶体管还包括在沿着沟道长度方向的沟道区域中具有不均匀杂质浓度分布的不对称杂质扩散区域，使得源极侧的杂质浓度设定为高于漏极侧的杂质浓度，第一源极区域下方的半导体衬底的一部分的杂质浓度低于不对称杂质扩散区域的源极侧的杂质浓度。

4. 发明授权

US5830788A Method for forming complementary MOS device having asymmetric region in channel region 失效
标题翻译：在沟道区域中形成具有不对称区域的互补MOS器件的方法
公开(公告)号：US5830788A
公开(公告)日：1998-11-03
申请号：US879579
申请日：1997-06-20
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823807 , H01L27/0922 , H01L29/0847 , H01L29/1045
摘要： A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region. The asymmetric MOS transistor further includes an asymmetric impurity diffusion region having a nonuniform impurity concentration distribution in the channel region along a channel length direction such that an impurity concentration on a source side is set to be higher than an impurity concentration on a drain side, and an impurity concentration of a portion of the semiconductor substrate beneath the first source region is lower than the impurity concentration on the source side of the asymmetric impurity diffusion region.
摘要翻译：一种互补半导体器件，包括：具有主表面的半导体衬底，掺杂有第一导电类型的杂质的第一区域和掺杂有第二导电类型的杂质的第二区域; 设置在第二区域上的第一MOS晶体管; 以及设置在第一区域上的第二MOS晶体管。在这种互补半导体器件中，第一MOS晶体管和第二MOS晶体管中的至少一个是与作为第一区域或第二区域的对应区域的导电类型相同导电类型的非对称MOS晶体管。非对称MOS晶体管还包括在沿着沟道长度方向的沟道区域中具有不均匀杂质浓度分布的不对称杂质扩散区域，使得源极侧的杂质浓度设定为高于漏极侧的杂质浓度，第一源极区域下方的半导体衬底的一部分的杂质浓度低于不对称杂质扩散区域的源极侧的杂质浓度。

5. 发明授权

US5675168A Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device 失效
标题翻译：具有偏离源极和漏极区域的栅极绝缘体区域的非对称MOS器件，以及包括这种MOS器件的ESD保护电路
公开(公告)号：US5675168A
公开(公告)日：1997-10-07
申请号：US415928
申请日：1995-04-03
申请人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
发明人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
IPC分类号： H01L27/02 , H01L27/088 , H01L29/08 , H01L29/78 , H01L23/60
CPC分类号： H01L27/0266 , H01L27/088 , H01L29/0847 , H01L29/7835 , H01L2924/0002
摘要： An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.
摘要翻译：公开了一种不对称MOS器件，其包括具有第一区域的表面的第一导电类型的半导体层和与第一区域偏移的第二区域; 位于所述半导体层表面的第一区域上的栅极绝缘体层; 位于栅极绝缘体层上的栅电极; 以及第二导电类型的源极区域和第二导电类型的漏极区域，每个位于该表面的第二区域下方的半导体层中。表面的第一区域和源区域的表面之间的区域的电阻小于表面的第一区域和漏极区域的表面之间的区域的电阻。

6. 发明授权

US08757338B2 Hydraulic shock absorber 有权
标题翻译：液压减震器
公开(公告)号：US08757338B2
公开(公告)日：2014-06-24
申请号：US13417436
申请日：2012-03-12
申请人： Eiko Miyasato , Masayuki Ishikawa , Tsuyoshi Mita , Akira Hiroki , Youji Takakuwa , Kouichi Matsuzaki , Toshio Minakuchi , Mariko Kessoku , Kodai Yoshinaga
发明人： Eiko Miyasato , Masayuki Ishikawa , Tsuyoshi Mita , Akira Hiroki , Youji Takakuwa , Kouichi Matsuzaki , Toshio Minakuchi , Mariko Kessoku , Kodai Yoshinaga
IPC分类号： F16F9/00
CPC分类号： F16F9/483 , F16F9/003
摘要： Provided is a shock absorber enabling stable stop by damping at a terminal of a stroke and covering demanded impact-absorbing models. The shock absorber has a piston chamber, a start part for piston movement, a decelerating part, and an end part for stopping the piston. The start part forms a curve to provide a diameter larger than a virtual tapered surface formed within a stroke range of the piston and to be outward to a central axis of the piston chamber. In the decelerating part, a variation of diameter reduction is increased with the result that the diameter becomes smaller than the tapered surface, and a curve is formed so the change in variation of diameter reduction reaches the maximum variation point and turns negative. In the end part, the variation of diameter reduction is decreased with the result that a curve which enables piston stopping by damping is formed.
摘要翻译：提供了一种减震器，能够通过在行程终端处的阻尼并且覆盖所需的冲击吸收模型而稳定地停止。减震器具有活塞室，活塞起动部，减速部以及止动活塞的端部。起始部分形成曲线以提供比在活塞的行程范围内形成的虚拟锥形表面的直径，并且向外延伸到活塞室的中心轴线。在减速部分中，直径减小的变化增加，其结果是直径变得小于锥形表面，并且形成曲线，使得直径减小的变化的变化达到最大变化点并变为负。在端部，直径减小的变化减小，结果形成能够通过阻尼而使活塞停止的曲线。

7. 发明申请

US20120247891A1 HYDRAULIC SHOCK ABSORBER 有权
标题翻译：液压减震器
公开(公告)号：US20120247891A1
公开(公告)日：2012-10-04
申请号：US13417436
申请日：2012-03-12
申请人： Eiko MIYASATO , Masayuki Ishikawa , Tsuyoshi Mita , Akira Hiroki , Youji Takakuwa , Kouichi Matsuzaki , Toshio Minakuchi , Mariko Kessoku , Kodai Yoshinaga
发明人： Eiko MIYASATO , Masayuki Ishikawa , Tsuyoshi Mita , Akira Hiroki , Youji Takakuwa , Kouichi Matsuzaki , Toshio Minakuchi , Mariko Kessoku , Kodai Yoshinaga
IPC分类号： F16F9/48 , F16F9/19
CPC分类号： F16F9/483 , F16F9/003
摘要： Provided is a shock absorber enabling stable stop by damping at a terminal of a stroke and covering demanded impact-absorbing models. The shock absorber has a piston chamber, a start part for piston movement, a decelerating part, and an end part for stopping the piston. The start part forms a curve to provide a diameter larger than a virtual tapered surface formed within a stroke range of the piston and to be outward to a central axis of the piston chamber. In the decelerating part, a variation of diameter reduction is increased with the result that the diameter becomes smaller than the tapered surface, and a curve is formed so the change in variation of diameter reduction reaches the maximum variation point and turns negative. In the end part, the variation of diameter reduction is decreased with the result that a curve which enables piston stopping by damping is formed.
摘要翻译：提供了一种减震器，能够通过在行程终端处的阻尼并且覆盖所需的冲击吸收模型而稳定地停止。减震器具有活塞室，活塞起动部，减速部以及止动活塞的端部。起始部分形成曲线以提供比在活塞的行程范围内形成的虚拟锥形表面的直径，并且向外延伸到活塞室的中心轴线。在减速部分中，直径减小的变化增加，其结果是直径变得小于锥形表面，并且形成曲线，使得直径减小的变化的变化达到最大变化点并变为负。在端部，直径减小的变化减小，结果形成能够通过阻尼而使活塞停止的曲线。

8. 发明申请

US20070017363A1 Fluid pressure cylinder apparatus having throttle valve 有权
标题翻译：具有节流阀的流体压力缸装置
公开(公告)号：US20070017363A1
公开(公告)日：2007-01-25
申请号：US11480931
申请日：2006-07-06
申请人： Akira Hiroki , Tadashi Ishii
发明人： Akira Hiroki , Tadashi Ishii
IPC分类号： F15B13/04
CPC分类号： F15B15/223
摘要： A cylindrically shaped valve rod is housed in a valve hole formed in a cylinder body in a manner so as to be rotatable around a center axis line, and a connecting hole having a first hole opening that is allowed to communicate with a first flow path hole, and a second hole opening that is allowed to communicate with a second flow path hole is formed in the valve rod. A flow adjusting groove that is extending in a circumferential direction around an outer periphery of the valve rod from a position of the first hole opening is formed, and the flow adjusting groove is formed such that a groove width gradually narrows toward a tip end side and the groove depth gradually shallows at the same time, so that the valve opening extent is adjusted along with rotating operation of the valve rod.
摘要翻译：圆柱形的阀杆容纳在形成在缸体中的阀孔中，以便能够围绕中心轴线旋转，以及具有第一孔口的连接孔，其允许与第一流路孔并且在阀杆中形成允许与第二流路孔连通的第二孔开口。形成有从第一开孔的位置沿圆周方向围绕阀杆的外周延伸的流量调节槽，并且流动调节槽形成为使得槽宽朝向前端侧逐渐变窄，槽深度同时逐渐变浅，因此阀门开度随着阀杆的旋转运行而调整。

9. 发明授权

US6031272A MOS type semiconductor device having an impurity diffusion layer with a nonuniform impurity concentration profile in a channel region 失效
标题翻译： MOS型半导体器件具有在沟道区中具有不均匀杂质浓度分布的杂质扩散层
公开(公告)号：US6031272A
公开(公告)日：2000-02-29
申请号：US836903
申请日：1997-07-16
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/786
CPC分类号： H01L29/66575 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate under a source diffusion layer is lower than the impurity concentration on a source side of a p-type impurity layer. Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage. Consequently, according to the present invention, a semiconductor device which can be operated at a low power consumption is realized.
摘要翻译： PCT No.PCT / JP95 / 02329 Sec。 371日期1997年7月16日 102（e）日期1997年7月16日PCT 1995年11月15日PCT PCT。出版物WO96 / 16432 日期1996年5月30日本发明的半导体器件形成为使得源极扩散层下的半导体衬底的杂质浓度低于p型杂质层的源极侧的杂质浓度。因此，在本发明的半导体器件中，与传统的LDC结构相比，源极和衬底之间的p-n结的结电容较小。通常，器件的速度与通过将负载电容和器件的当前值的反相相乘得到的乘积成比例。因此，在将本发明应用于其中向源极和基板之间的区域施加电压的NAND型CMOS电路的电路的情况下，器件的速度不降低。另一方面，器件的功耗与通过将负载电容和施加电压的平方相乘获得的乘积成比例。因此，根据本发明，实现了能够以低功耗工作的半导体装置。

10. 发明授权

US5808347A MIS transistor with gate sidewall insulating layer 失效
标题翻译：具有栅极侧壁绝缘层的MIS晶体管
公开(公告)号：US5808347A
公开(公告)日：1998-09-15
申请号：US23122
申请日：1993-02-26
申请人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
发明人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/336 , H01L29/76 , H01L27/088 , H01L29/94
CPC分类号： H01L29/6659 , H01L29/6656 , Y10S257/90
摘要： A MIS transistor has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.
摘要翻译： MIS晶体管具有第一导电类型的半导体衬底; 选择性地形成在半导体衬底上的栅极绝缘膜和栅电极; 绝缘膜，形成在所述栅电极的侧表面和所述半导体衬底上; 所述第一栅极侧壁层设置在所述绝缘膜的上表面和侧表面上并且具有大于所述绝缘膜的介电常数的介电常数，所述第一栅极侧壁层的高度小于所述栅电极的高度; 以及由覆盖所述第一栅极侧壁层的绝缘膜构成的第二栅极侧壁层。该MIS晶体管可以通过采用自对准的已知LSI生产技术制造，而不增加该工艺步骤的数量。

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