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1. 发明授权

US07271449B2 Semiconductor device having triple-well structure 有权
标题翻译：具有三重结构的半导体器件
公开(公告)号：US07271449B2
公开(公告)日：2007-09-18
申请号：US11119849
申请日：2005-05-03
申请人： Makoto Misaki , Kazumi Kurimoto
发明人： Makoto Misaki , Kazumi Kurimoto
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0928 , H01L21/823892
摘要： A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.
摘要翻译：半导体器件具有第一导电类型的半导体衬底，形成为从半导体衬底的表面向其内部延伸的第一导电类型的第一阱区，第二导电性的一对第二阱区，形成为从半导体衬底的表面朝向其内部延伸以将第一阱区域夹在其间的方式，以及形成在第一阱区域和第二阱区域中的第二阱区域的第三阱区域，半导体衬底中的一对第二阱区。第三阱区将一对第二阱区彼此电连接。第一阱区域的至少一部分连接到半导体衬底的不形成第三阱区域的区域。

2. 发明申请

US20060086990A1 Semiconductor device and fabrication method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060086990A1
公开(公告)日：2006-04-27
申请号：US11119849
申请日：2005-05-03
申请人： Makoto Misaki , Kazumi Kurimoto
发明人： Makoto Misaki , Kazumi Kurimoto
IPC分类号： H01L29/76
CPC分类号： H01L27/0928 , H01L21/823892
摘要： A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.
摘要翻译：半导体器件具有第一导电类型的半导体衬底，形成为从半导体衬底的表面向其内部延伸的第一导电类型的第一阱区，第二导电性的一对第二阱区，形成为从半导体衬底的表面朝向其内部延伸以将第一阱区域夹在其间的方式形成，并且形成在第一阱区域和第二阱区域中的第二导电类型的第三阱区域半导体衬底中的一对第二阱区。第三阱区将一对第二阱区彼此电连接。第一阱区域的至少一部分连接到半导体衬底的不形成第三阱区域的区域。

3. 发明授权

US07696544B2 Solid-state image sensing device and manufacturing method thereof 失效
标题翻译：固态摄像装置及其制造方法
公开(公告)号：US07696544B2
公开(公告)日：2010-04-13
申请号：US11700000
申请日：2007-01-31
申请人： Makoto Misaki , Masafumi Tsutsui
发明人： Makoto Misaki , Masafumi Tsutsui
IPC分类号： H01L31/062
CPC分类号： H01L27/1463 , H01L27/14603 , H01L27/14689
摘要： Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the transfer gate is embedded in the device isolation region. The buried gate includes a gate dielectric film and gate electrode formed in a trench of the semiconductor substrate.
摘要翻译：每个具有形成在半导体衬底11中的电荷存储部分的像素部分和用于转移存储在电荷存储部分中的电荷的传输栅极通过半导体衬底中的器件隔离区域相互隔离。电连接到传输门的掩埋栅极嵌入在器件隔离区域中。掩埋栅极包括形成在半导体衬底的沟槽中的栅极电介质膜和栅电极。

4. 发明申请

US20070272958A1 Solid-state image sensing device and manufacturing method thereof 失效
标题翻译：固态摄像装置及其制造方法
公开(公告)号：US20070272958A1
公开(公告)日：2007-11-29
申请号：US11700000
申请日：2007-01-31
申请人： Makoto Misaki , Masafumi Tsutsui
发明人： Makoto Misaki , Masafumi Tsutsui
IPC分类号： H01L31/113
CPC分类号： H01L27/1463 , H01L27/14603 , H01L27/14689
摘要： Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the transfer gate is embedded in the device isolation region. The buried gate includes a gate dielectric film and gate electrode formed in a trench of the semiconductor substrate.
摘要翻译：每个具有形成在半导体衬底11中的电荷存储部分的像素部分和用于转移存储在电荷存储部分中的电荷的传输栅极通过半导体衬底中的器件隔离区域相互隔离。电连接到传输门的掩埋栅极嵌入在器件隔离区域中。掩埋栅极包括形成在半导体衬底的沟槽中的栅极电介质膜和栅电极。

5. 发明授权

US07304350B2 Threshold voltage control layer in a semiconductor device 有权
标题翻译：半导体器件中的阈值电压控制层
公开(公告)号：US07304350B2
公开(公告)日：2007-12-04
申请号：US11410047
申请日：2006-04-25
申请人： Makoto Misaki
发明人： Makoto Misaki
IPC分类号： H01L29/94
CPC分类号： H01L29/6659 , H01L21/2253 , H01L21/26586 , H01L29/1079 , H01L29/7833 , Y10S257/927
摘要： A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto. The junction surface between the threshold voltage control layer and the extension region has an upwardly protruding configuration.
摘要翻译：半导体器件具有第一导电类型的阱区，并且形成在半导体衬底的上部，连续形成在半导体衬底的阱区上的栅极绝缘膜和栅电极，用于控制半导体衬底的阈值电压控制层形成在位于栅极电极下方的阱区域的部分中的阈值电压，并且其中第一导电类型的杂质在比阱区域浅的位置处具有浓度峰值，具有第二导电类型的延伸区域和形成在所述阱区中，以位于所述阱区的位于所述栅极电极的栅极长度方向和所述阈值电压控制层的两端部下方的各个所述各部分之间，以及源极和漏极区域，第二导电类型，并以与其连接的关系形成在延伸层之外。阈值电压控制层与延伸区域之间的结面具有向上突出的构型。

6. 发明申请

US20070054456A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070054456A1
公开(公告)日：2007-03-08
申请号：US11410047
申请日：2006-04-25
申请人： Makoto Misaki
发明人： Makoto Misaki
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/2253 , H01L21/26586 , H01L29/1079 , H01L29/7833 , Y10S257/927
摘要： A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto. The junction surface between the threshold voltage control layer and the extension region has an upwardly protruding configuration.
摘要翻译：半导体器件具有第一导电类型的阱区，并且形成在半导体衬底的上部，连续形成在半导体衬底的阱区上的栅极绝缘膜和栅电极，用于控制半导体衬底的阈值电压控制层形成在位于栅电极下方的阱区的部分中的阈值电压，其中第一导电类型的杂质在比阱区浅的位置具有浓度峰，具有第二导电类型的延伸区和形成在所述阱区中，以位于所述阱区的位于所述栅极电极的栅极长度方向和所述阈值电压控制层的两端部下方的各个所述各部分之间，以及源极和漏极区域，第二导电类型，并以与其连接的关系形成在延伸层之外。阈值电压控制层与延伸区域之间的结面具有向上突出的构型。

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