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1. 发明授权

US5675168A Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device 失效
标题翻译：具有偏离源极和漏极区域的栅极绝缘体区域的非对称MOS器件，以及包括这种MOS器件的ESD保护电路
公开(公告)号：US5675168A
公开(公告)日：1997-10-07
申请号：US415928
申请日：1995-04-03
申请人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
发明人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
IPC分类号： H01L27/02 , H01L27/088 , H01L29/08 , H01L29/78 , H01L23/60
CPC分类号： H01L27/0266 , H01L27/088 , H01L29/0847 , H01L29/7835 , H01L2924/0002
摘要： An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.
摘要翻译：公开了一种不对称MOS器件，其包括具有第一区域的表面的第一导电类型的半导体层和与第一区域偏移的第二区域; 位于所述半导体层表面的第一区域上的栅极绝缘体层; 位于栅极绝缘体层上的栅电极; 以及第二导电类型的源极区域和第二导电类型的漏极区域，每个位于该表面的第二区域下方的半导体层中。表面的第一区域和源区域的表面之间的区域的电阻小于表面的第一区域和漏极区域的表面之间的区域的电阻。

2. 发明授权

US5514893A Semiconductor device for protecting an internal circuit from electrostatic damage 失效
标题翻译：用于保护内部电路免受静电损坏的半导体器件
公开(公告)号：US5514893A
公开(公告)日：1996-05-07
申请号：US207426
申请日：1994-03-08
申请人： Isao Miyanaga , Kazumi Kurimoto , Atsushi Hori , Shinji Odanaka
发明人： Isao Miyanaga , Kazumi Kurimoto , Atsushi Hori , Shinji Odanaka
IPC分类号： H01L27/02 , H03K19/003 , H01L23/62 , H02H3/20 , H02H9/00 , H03K17/60
CPC分类号： H01L27/0259 , H01L27/0266 , H03K19/00315
摘要： A semiconductor device includes an input/output terminal, an internal circuit connected to the input/output terminal, a first terminal for providing a first electrical potential, and a second terminal for providing a second electrical potential which is lower than the first electrical potential, the device further including: a first n-channel MOS transistor having a drain connected to the input/output terminal, a source connected to the second terminal, and a gate to be electrically connected to the first terminal; and a first switching element for switching between an electrically conductive state and a non-conductive state between the drain and the gate of the first n-channel MOS transistor, the switching element forming the electrically conductive state between the drain and the gate of the first n-channel MOS transistor when 1) a surge voltage lower than the first electrical potential is applied to the input/output terminal, and 2) an electrical potential difference between the drain and the gate of the first n-channel MOS transistor exceeds a predetermined voltage lower than a breakdown voltage of the gate of the first n-channel MOS transistor. The formation of the electrically conductive state prevents the gate oxide of the first n-channel MOS transistor from being damaged.
摘要翻译：半导体器件包括输入/输出端子，连接到输入/输出端子的内部电路，用于提供第一电位的第一端子和用于提供低于第一电位的第二电位的第二端子，该器件还包括：第一n沟道MOS晶体管，具有连接到输入/输出端子的漏极，连接到第二端子的源极和与第一端子电连接的栅极; 以及用于在第一n沟道MOS晶体管的漏极和栅极之间切换导电状态和非导通状态的第一开关元件，所述开关元件在第一N沟道MOS晶体管的漏极和栅极之间形成导电状态 n沟道MOS晶体管，当1）低于第一电位的浪涌电压被施加到输入/输出端时，以及2）第一n沟道MOS晶体管的漏极和栅极之间的电位差超过预定的电压低于第一n沟道MOS晶体管的栅极的击穿电压。导电状态的形成防止了第一n沟道MOS晶体管的栅极氧化物被损坏。

3. 发明授权

US5610430A Semiconductor device having reduced gate overlapping capacitance 失效
标题翻译：具有减小的栅极重叠电容的半导体器件
公开(公告)号：US5610430A
公开(公告)日：1997-03-11
申请号：US494384
申请日：1995-06-26
申请人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Hiroyuki Umimoto
发明人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Hiroyuki Umimoto
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/423 , H01L29/76 , H01L27/088 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823857 , H01L29/0847 , H01L29/42368 , H01L21/26586 , H01L29/66545 , Y10S257/90
摘要： The semiconductor device of the invention includes: a semiconductor substrate of a first conductivity type; a gate insulating film formed on a selected region on a main surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; and a source region and a drain region which are formed of high-concentration impurity diffusion layers of a second conductivity type in the semiconductor substrate. In the semiconductor device, a thickness of both end portions of the gate insulating film is larger than a thickness of a center portion of the gate insulating film, and each of the source region and the drain region includes a first portion located under both end-portions of the gate insulating film and a second portion having a thickness equal to or larger than a thickness of the first portion. An impurity concentration in the first portion is substantially equal to an impurity concentration in the second portion.
摘要翻译：本发明的半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的主表面上的选定区域上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及在半导体衬底中由第二导电类型的高浓度杂质扩散层形成的源极区和漏极区。在半导体装置中，栅极绝缘膜的两端部的厚度大于栅极绝缘膜的中央部的厚度，源区域和漏极区域中的每一个包括位于两端部的第一部分，栅极绝缘膜的一部分和第二部分的厚度等于或大于第一部分的厚度。第一部分中的杂质浓度基本上等于第二部分中的杂质浓度。

4. 发明授权

US5386133A LDD FET with polysilicon sidewalls 失效
标题翻译： LDD FET具有多晶硅侧壁
公开(公告)号：US5386133A
公开(公告)日：1995-01-31
申请号：US225098
申请日：1994-04-08
申请人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
发明人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/66545 , Y10S257/90
摘要： An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished. Also, by forming the second conductivity type diffusion layer 7A on the sides of the gate electrode 5 through the medium of the thin insulating film 6 to be above the low concentration diffusion layer 3 and further contacting the low concentration diffusion layer 3, the high electrical field within the low concentration diffusion layer 3 is sufficiently ameliorated, generation of hot carriers is suppressed, and resistance to degradation is improved. Moreover, by controlling the high resistance second conductivity typetype diffusion layer 7 A at the sides of the gate electrode 5, the source resistance is decreased and driving capabilities are improved. At the same time the contact region of the source-drain electrode is miniaturized.
摘要翻译：本发明的目的是提供一种能够抑制热载流子劣化，提高驱动能力并且还使得能够使亚微米区域小型化的MOS半导体器件; 及其制造方法。通过在第二导电型低浓度扩散层3之间的第一导电型半导体衬底1的一个主表面上的栅极氧化膜4的介质形成栅电极5，使有效沟道长度大致等于栅极长度，实现了对亚微米区域的小型化和小型化。此外，通过在栅电极5的侧面上形成第二导电型扩散层7A，通过薄绝缘膜6的介质在低浓度扩散层3的上方进一步与低浓度扩散层3接触，充分改善了低浓度扩散层3内的场，抑制了热载流子的产生，提高了耐劣化性。此外，通过控制栅电极5侧的高电阻第二导电类型扩散层7A，源电阻降低，驱动能力提高。同时源极 - 漏极电极的接触区域被小型化。

5. 发明授权

US5808347A MIS transistor with gate sidewall insulating layer 失效
标题翻译：具有栅极侧壁绝缘层的MIS晶体管
公开(公告)号：US5808347A
公开(公告)日：1998-09-15
申请号：US23122
申请日：1993-02-26
申请人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
发明人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/336 , H01L29/76 , H01L27/088 , H01L29/94
CPC分类号： H01L29/6659 , H01L29/6656 , Y10S257/90
摘要： A MIS transistor has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.
摘要翻译： MIS晶体管具有第一导电类型的半导体衬底; 选择性地形成在半导体衬底上的栅极绝缘膜和栅电极; 绝缘膜，形成在所述栅电极的侧表面和所述半导体衬底上; 所述第一栅极侧壁层设置在所述绝缘膜的上表面和侧表面上并且具有大于所述绝缘膜的介电常数的介电常数，所述第一栅极侧壁层的高度小于所述栅电极的高度; 以及由覆盖所述第一栅极侧壁层的绝缘膜构成的第二栅极侧壁层。该MIS晶体管可以通过采用自对准的已知LSI生产技术制造，而不增加该工艺步骤的数量。

6. 发明授权

US5518944A MOS transistor and its fabricating method 失效
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US5518944A
公开(公告)日：1996-05-21
申请号：US308756
申请日：1994-09-19
申请人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
发明人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/66545 , Y10S257/90
摘要： An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished. Also, by forming the second conductivity type diffusion layer 7A on the sides of the gate electrode 5 through the medium of the thin insulating film 6 to be above the low concentration diffusion layer 3 and further contacting the low concentration diffusion layer 3, the high electrical field within the low concentration diffusion layer 3 is sufficiently ameliorated, generation of hot carriers is suppressed, and resistance to degradation is improved. Moreover, by controlling the high resistance second conductivity typetype diffusion layer 7 A at the sides of the gate electrode 5, the source resistance is decreased and driving capabilities are improved. At the same time the contact region of the source-drain electrode is miniaturized.
摘要翻译：本发明的目的是提供一种能够抑制热载流子劣化，提高驱动能力并且还使得能够使亚微米区域小型化的MOS半导体器件; 及其制造方法。通过在第二导电型低浓度扩散层3之间的第一导电型半导体衬底1的一个主表面上的栅极氧化膜4的介质形成栅电极5，使有效沟道长度大致等于栅极长度，实现了对亚微米区域的小型化和小型化。此外，通过在栅电极5的侧面上形成第二导电型扩散层7A，通过薄绝缘膜6的介质在低浓度扩散层3的上方进一步接触低浓度扩散层3，充分改善了低浓度扩散层3内的场，抑制了热载流子的产生，提高了耐劣化性。此外，通过控制栅电极5侧的高电阻第二导电类型扩散层7A，源电阻降低，驱动能力提高。同时源极 - 漏极电极的接触区域被小型化。

7. 发明授权

US5512771A MOS type semiconductor device having a low concentration impurity diffusion region 失效
标题翻译：具有低浓度杂质扩散区的MOS型半导体器件
公开(公告)号：US5512771A
公开(公告)日：1996-04-30
申请号：US147866
申请日：1993-11-04
申请人： Akira Hiroki , Kazumi Kurimoto , Shinji Odanaka
发明人： Akira Hiroki , Kazumi Kurimoto , Shinji Odanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/823857 , H01L27/0928 , H01L29/6656 , H01L29/78 , H01L29/7836 , H01L21/26586
摘要： An MOS type semiconductor device comprises a semiconductor substrate including a p-type region doped with p-type impurities and having a surface and an MOS transistor formed in the p-type region, the MOS transistor including: an n-type source region formed in the p-type region; an n-type drain region formed in the p-type region and separated from the n-type source region by a predetermined distance; a channel region formed in the p-type region and located between the n-type source and drain regions; a pair of n-type impurity diffusion regions formed on both sides of the channel region and having an impurity concentration lower than that of the n-type source region; a gate insulating film formed on the surface of the semiconductor substrate, the gate insulating film directly covering the channel region and the pair of n-type impurity diffusion regions; a gate electrode formed on the gate insulating film; and side walls formed on the sides of the gate electrode, wherein each of the side walls has a bottom portion extending along the surface of the semiconductor substrate from each side of the gate electrode, and each of the n-type source and drain regions has a first portion covered with the bottom portion of the side wall and a second portion not covered with the bottom portion, a thickness of the first portion being smaller than that of the second portion. A method for fabricating such an MOS type semiconductor device is also provided.
摘要翻译：一种MOS型半导体器件包括：半导体衬底，包括掺杂有p型杂质的p型区域，并且具有形成在p型区域中的表面和MOS晶体管，所述MOS晶体管包括：n型源极区，形成在 p型区域; 形成在p型区域并与n型源极区域隔开预定距离的n型漏极区域; 形成在p型区域并位于n型源区和漏区之间的沟道区; 形成在沟道区两侧的杂质浓度低于n型源区的杂质浓度的一对n型杂质扩散区; 形成在所述半导体衬底的表面上的栅极绝缘膜，所述栅极绝缘膜直接覆盖所述沟道区域和所述一对n型杂质扩散区域; 形成在栅极绝缘膜上的栅电极; 以及形成在栅电极的侧面上的侧壁，其中每个侧壁具有从栅电极的每一侧沿着半导体衬底的表面延伸的底部，并且n型源极和漏极区中的每一个具有覆盖有所述侧壁的底部的第一部分和未被所述底部部分覆盖的第二部分，所述第一部分的厚度小于所述第二部分的厚度。还提供了制造这种MOS型半导体器件的方法。

8. 发明授权

US5221632A Method of proudcing a MIS transistor 失效
标题翻译：引导MIS晶体管的方法
公开(公告)号：US5221632A
公开(公告)日：1993-06-22
申请号：US780760
申请日：1991-10-25
申请人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
发明人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/6656 , Y10S257/90
摘要： A MIS transistor, has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.
摘要翻译：一种MIS晶体管，具有第一导电类型的半导体衬底; 选择性地形成在半导体衬底上的栅极绝缘膜和栅电极; 绝缘膜，形成在所述栅电极的侧表面和所述半导体衬底上; 所述第一栅极侧壁层设置在所述绝缘膜的上表面和侧表面上并且具有大于所述绝缘膜的介电常数的介电常数，所述第一栅极侧壁层的高度小于所述栅电极的高度; 以及由覆盖所述第一栅极侧壁层的绝缘膜构成的第二栅极侧壁层。该MIS晶体管可以通过采用自对准的已知LSI生产技术制造，而不增加该工艺步骤的数量。

9. 发明授权

US06184553B2 Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device 失效
公开(公告)号：US06184553B2
公开(公告)日：2001-02-06
申请号：US09325772
申请日：1999-06-04
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： H07L27115
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

10. 发明授权

US06051860A Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit 失效
标题翻译：非易失性半导体存储器件及其制造方法和半导体集成电路
公开(公告)号：US06051860A
公开(公告)日：2000-04-18
申请号：US8572
申请日：1998-01-16
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/72
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.
摘要翻译：在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道区域有三重结构。因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。在第一表面区域也形成高电场。结果，电子注入浮栅的效率大大增加。

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