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1. 发明授权

US5386133A LDD FET with polysilicon sidewalls 失效
标题翻译： LDD FET具有多晶硅侧壁
公开(公告)号：US5386133A
公开(公告)日：1995-01-31
申请号：US225098
申请日：1994-04-08
申请人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
发明人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/66545 , Y10S257/90
摘要： An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished. Also, by forming the second conductivity type diffusion layer 7A on the sides of the gate electrode 5 through the medium of the thin insulating film 6 to be above the low concentration diffusion layer 3 and further contacting the low concentration diffusion layer 3, the high electrical field within the low concentration diffusion layer 3 is sufficiently ameliorated, generation of hot carriers is suppressed, and resistance to degradation is improved. Moreover, by controlling the high resistance second conductivity typetype diffusion layer 7 A at the sides of the gate electrode 5, the source resistance is decreased and driving capabilities are improved. At the same time the contact region of the source-drain electrode is miniaturized.
摘要翻译：本发明的目的是提供一种能够抑制热载流子劣化，提高驱动能力并且还使得能够使亚微米区域小型化的MOS半导体器件; 及其制造方法。通过在第二导电型低浓度扩散层3之间的第一导电型半导体衬底1的一个主表面上的栅极氧化膜4的介质形成栅电极5，使有效沟道长度大致等于栅极长度，实现了对亚微米区域的小型化和小型化。此外，通过在栅电极5的侧面上形成第二导电型扩散层7A，通过薄绝缘膜6的介质在低浓度扩散层3的上方进一步与低浓度扩散层3接触，充分改善了低浓度扩散层3内的场，抑制了热载流子的产生，提高了耐劣化性。此外，通过控制栅电极5侧的高电阻第二导电类型扩散层7A，源电阻降低，驱动能力提高。同时源极 - 漏极电极的接触区域被小型化。

2. 发明授权

US5675168A Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device 失效
标题翻译：具有偏离源极和漏极区域的栅极绝缘体区域的非对称MOS器件，以及包括这种MOS器件的ESD保护电路
公开(公告)号：US5675168A
公开(公告)日：1997-10-07
申请号：US415928
申请日：1995-04-03
申请人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
发明人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
IPC分类号： H01L27/02 , H01L27/088 , H01L29/08 , H01L29/78 , H01L23/60
CPC分类号： H01L27/0266 , H01L27/088 , H01L29/0847 , H01L29/7835 , H01L2924/0002
摘要： An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.
摘要翻译：公开了一种不对称MOS器件，其包括具有第一区域的表面的第一导电类型的半导体层和与第一区域偏移的第二区域; 位于所述半导体层表面的第一区域上的栅极绝缘体层; 位于栅极绝缘体层上的栅电极; 以及第二导电类型的源极区域和第二导电类型的漏极区域，每个位于该表面的第二区域下方的半导体层中。表面的第一区域和源区域的表面之间的区域的电阻小于表面的第一区域和漏极区域的表面之间的区域的电阻。

3. 发明授权

US5808347A MIS transistor with gate sidewall insulating layer 失效
标题翻译：具有栅极侧壁绝缘层的MIS晶体管
公开(公告)号：US5808347A
公开(公告)日：1998-09-15
申请号：US23122
申请日：1993-02-26
申请人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
发明人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/336 , H01L29/76 , H01L27/088 , H01L29/94
CPC分类号： H01L29/6659 , H01L29/6656 , Y10S257/90
摘要： A MIS transistor has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.
摘要翻译： MIS晶体管具有第一导电类型的半导体衬底; 选择性地形成在半导体衬底上的栅极绝缘膜和栅电极; 绝缘膜，形成在所述栅电极的侧表面和所述半导体衬底上; 所述第一栅极侧壁层设置在所述绝缘膜的上表面和侧表面上并且具有大于所述绝缘膜的介电常数的介电常数，所述第一栅极侧壁层的高度小于所述栅电极的高度; 以及由覆盖所述第一栅极侧壁层的绝缘膜构成的第二栅极侧壁层。该MIS晶体管可以通过采用自对准的已知LSI生产技术制造，而不增加该工艺步骤的数量。

4. 发明授权

US5518944A MOS transistor and its fabricating method 失效
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US5518944A
公开(公告)日：1996-05-21
申请号：US308756
申请日：1994-09-19
申请人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
发明人： Akira Hiroki , Shinji Odanaka , Kazumi Kurimoto
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/66545 , Y10S257/90
摘要： An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished. Also, by forming the second conductivity type diffusion layer 7A on the sides of the gate electrode 5 through the medium of the thin insulating film 6 to be above the low concentration diffusion layer 3 and further contacting the low concentration diffusion layer 3, the high electrical field within the low concentration diffusion layer 3 is sufficiently ameliorated, generation of hot carriers is suppressed, and resistance to degradation is improved. Moreover, by controlling the high resistance second conductivity typetype diffusion layer 7 A at the sides of the gate electrode 5, the source resistance is decreased and driving capabilities are improved. At the same time the contact region of the source-drain electrode is miniaturized.
摘要翻译：本发明的目的是提供一种能够抑制热载流子劣化，提高驱动能力并且还使得能够使亚微米区域小型化的MOS半导体器件; 及其制造方法。通过在第二导电型低浓度扩散层3之间的第一导电型半导体衬底1的一个主表面上的栅极氧化膜4的介质形成栅电极5，使有效沟道长度大致等于栅极长度，实现了对亚微米区域的小型化和小型化。此外，通过在栅电极5的侧面上形成第二导电型扩散层7A，通过薄绝缘膜6的介质在低浓度扩散层3的上方进一步接触低浓度扩散层3，充分改善了低浓度扩散层3内的场，抑制了热载流子的产生，提高了耐劣化性。此外，通过控制栅电极5侧的高电阻第二导电类型扩散层7A，源电阻降低，驱动能力提高。同时源极 - 漏极电极的接触区域被小型化。

5. 发明授权

US5512771A MOS type semiconductor device having a low concentration impurity diffusion region 失效
标题翻译：具有低浓度杂质扩散区的MOS型半导体器件
公开(公告)号：US5512771A
公开(公告)日：1996-04-30
申请号：US147866
申请日：1993-11-04
申请人： Akira Hiroki , Kazumi Kurimoto , Shinji Odanaka
发明人： Akira Hiroki , Kazumi Kurimoto , Shinji Odanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/823857 , H01L27/0928 , H01L29/6656 , H01L29/78 , H01L29/7836 , H01L21/26586
摘要： An MOS type semiconductor device comprises a semiconductor substrate including a p-type region doped with p-type impurities and having a surface and an MOS transistor formed in the p-type region, the MOS transistor including: an n-type source region formed in the p-type region; an n-type drain region formed in the p-type region and separated from the n-type source region by a predetermined distance; a channel region formed in the p-type region and located between the n-type source and drain regions; a pair of n-type impurity diffusion regions formed on both sides of the channel region and having an impurity concentration lower than that of the n-type source region; a gate insulating film formed on the surface of the semiconductor substrate, the gate insulating film directly covering the channel region and the pair of n-type impurity diffusion regions; a gate electrode formed on the gate insulating film; and side walls formed on the sides of the gate electrode, wherein each of the side walls has a bottom portion extending along the surface of the semiconductor substrate from each side of the gate electrode, and each of the n-type source and drain regions has a first portion covered with the bottom portion of the side wall and a second portion not covered with the bottom portion, a thickness of the first portion being smaller than that of the second portion. A method for fabricating such an MOS type semiconductor device is also provided.
摘要翻译：一种MOS型半导体器件包括：半导体衬底，包括掺杂有p型杂质的p型区域，并且具有形成在p型区域中的表面和MOS晶体管，所述MOS晶体管包括：n型源极区，形成在 p型区域; 形成在p型区域并与n型源极区域隔开预定距离的n型漏极区域; 形成在p型区域并位于n型源区和漏区之间的沟道区; 形成在沟道区两侧的杂质浓度低于n型源区的杂质浓度的一对n型杂质扩散区; 形成在所述半导体衬底的表面上的栅极绝缘膜，所述栅极绝缘膜直接覆盖所述沟道区域和所述一对n型杂质扩散区域; 形成在栅极绝缘膜上的栅电极; 以及形成在栅电极的侧面上的侧壁，其中每个侧壁具有从栅电极的每一侧沿着半导体衬底的表面延伸的底部，并且n型源极和漏极区中的每一个具有覆盖有所述侧壁的底部的第一部分和未被所述底部部分覆盖的第二部分，所述第一部分的厚度小于所述第二部分的厚度。还提供了制造这种MOS型半导体器件的方法。

6. 发明授权

US5221632A Method of proudcing a MIS transistor 失效
标题翻译：引导MIS晶体管的方法
公开(公告)号：US5221632A
公开(公告)日：1993-06-22
申请号：US780760
申请日：1991-10-25
申请人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
发明人： Kazumi Kurimoto , Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/6656 , Y10S257/90
摘要： A MIS transistor, has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.
摘要翻译：一种MIS晶体管，具有第一导电类型的半导体衬底; 选择性地形成在半导体衬底上的栅极绝缘膜和栅电极; 绝缘膜，形成在所述栅电极的侧表面和所述半导体衬底上; 所述第一栅极侧壁层设置在所述绝缘膜的上表面和侧表面上并且具有大于所述绝缘膜的介电常数的介电常数，所述第一栅极侧壁层的高度小于所述栅电极的高度; 以及由覆盖所述第一栅极侧壁层的绝缘膜构成的第二栅极侧壁层。该MIS晶体管可以通过采用自对准的已知LSI生产技术制造，而不增加该工艺步骤的数量。

7. 发明授权

US06355963B1 MOS type semiconductor device having an impurity diffusion layer 有权
标题翻译：具有杂质扩散层的MOS型半导体器件
公开(公告)号：US06355963B1
公开(公告)日：2002-03-12
申请号：US09514924
申请日：2000-02-28
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H02L2994
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/66575 , H01L29/66659
摘要： A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate (1) under a source diffusion layer (2) is lower than the impurity concentration on a source side of a p-type impurity diffusion layer (6). Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage. Consequently, according to the present invention, a semiconductor device which can be operated at a low power consumption is realized.
摘要翻译：本发明的半导体器件形成为使得源极扩散层（2）下方的半导体衬底（1）的杂质浓度低于p型杂质扩散层（6）的源极侧的杂质浓度。因此，在本发明的半导体器件中，与传统的LDC结构相比，源极和衬底之间的p-n结的结电容较小。通常，器件的速度与通过将负载电容和器件的当前值的反相相乘得到的乘积成比例。因此，在将本发明应用于其中向源极和基板之间的区域施加电压的NAND型CMOS电路的电路的情况下，器件的速度不降低。另一方面，器件的功耗与通过将负载电容和施加电压的平方相乘获得的乘积成比例。因此，根据本发明，实现了能够以低功耗工作的半导体装置。

8. 发明授权

US6031268A Complementary semiconductor device and method for producing the same 失效
标题翻译：互补半导体器件及其制造方法
公开(公告)号：US6031268A
公开(公告)日：2000-02-29
申请号：US121350
申请日：1998-07-23
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10 , H01L29/76
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823807 , H01L27/0922 , H01L29/0847 , H01L29/1045
摘要： A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region. The asymmetric MOS transistor further includes an asymmetric impurity diffusion region having a nonuniform impurity concentration distribution in the channel region along a channel length direction such that an impurity concentration on a source side is set to be higher than an impurity concentration on a drain side, and an impurity concentration of a portion of the semiconductor substrate beneath the first source region is lower than the impurity concentration on the source side of the asymmetric impurity diffusion region.
摘要翻译：一种互补半导体器件，包括：具有主表面的半导体衬底，掺杂有第一导电类型的杂质的第一区域和掺杂有第二导电类型的杂质的第二区域; 设置在第二区域上的第一MOS晶体管; 以及设置在第一区域上的第二MOS晶体管。在这种互补半导体器件中，第一MOS晶体管和第二MOS晶体管中的至少一个是与作为第一区域或第二区域的对应区域的导电类型相同导电类型的非对称MOS晶体管。非对称MOS晶体管还包括在沿着沟道长度方向的沟道区域中具有不均匀杂质浓度分布的不对称杂质扩散区域，使得源极侧的杂质浓度设定为高于漏极侧的杂质浓度，第一源极区域下方的半导体衬底的一部分的杂质浓度低于不对称杂质扩散区域的源极侧的杂质浓度。

9. 发明授权

US5830788A Method for forming complementary MOS device having asymmetric region in channel region 失效
标题翻译：在沟道区域中形成具有不对称区域的互补MOS器件的方法
公开(公告)号：US5830788A
公开(公告)日：1998-11-03
申请号：US879579
申请日：1997-06-20
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823807 , H01L27/0922 , H01L29/0847 , H01L29/1045
摘要： A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region. The asymmetric MOS transistor further includes an asymmetric impurity diffusion region having a nonuniform impurity concentration distribution in the channel region along a channel length direction such that an impurity concentration on a source side is set to be higher than an impurity concentration on a drain side, and an impurity concentration of a portion of the semiconductor substrate beneath the first source region is lower than the impurity concentration on the source side of the asymmetric impurity diffusion region.
摘要翻译：一种互补半导体器件，包括：具有主表面的半导体衬底，掺杂有第一导电类型的杂质的第一区域和掺杂有第二导电类型的杂质的第二区域; 设置在第二区域上的第一MOS晶体管; 以及设置在第一区域上的第二MOS晶体管。在这种互补半导体器件中，第一MOS晶体管和第二MOS晶体管中的至少一个是与作为第一区域或第二区域的对应区域的导电类型相同导电类型的非对称MOS晶体管。非对称MOS晶体管还包括在沿着沟道长度方向的沟道区域中具有不均匀杂质浓度分布的不对称杂质扩散区域，使得源极侧的杂质浓度设定为高于漏极侧的杂质浓度，第一源极区域下方的半导体衬底的一部分的杂质浓度低于不对称杂质扩散区域的源极侧的杂质浓度。

10. 发明授权

US6031272A MOS type semiconductor device having an impurity diffusion layer with a nonuniform impurity concentration profile in a channel region 失效
标题翻译： MOS型半导体器件具有在沟道区中具有不均匀杂质浓度分布的杂质扩散层
公开(公告)号：US6031272A
公开(公告)日：2000-02-29
申请号：US836903
申请日：1997-07-16
申请人： Akira Hiroki , Shinji Odanaka
发明人： Akira Hiroki , Shinji Odanaka
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/786
CPC分类号： H01L29/66575 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate under a source diffusion layer is lower than the impurity concentration on a source side of a p-type impurity layer. Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage. Consequently, according to the present invention, a semiconductor device which can be operated at a low power consumption is realized.
摘要翻译： PCT No.PCT / JP95 / 02329 Sec。 371日期1997年7月16日 102（e）日期1997年7月16日PCT 1995年11月15日PCT PCT。出版物WO96 / 16432 日期1996年5月30日本发明的半导体器件形成为使得源极扩散层下的半导体衬底的杂质浓度低于p型杂质层的源极侧的杂质浓度。因此，在本发明的半导体器件中，与传统的LDC结构相比，源极和衬底之间的p-n结的结电容较小。通常，器件的速度与通过将负载电容和器件的当前值的反相相乘得到的乘积成比例。因此，在将本发明应用于其中向源极和基板之间的区域施加电压的NAND型CMOS电路的电路的情况下，器件的速度不降低。另一方面，器件的功耗与通过将负载电容和施加电压的平方相乘获得的乘积成比例。因此，根据本发明，实现了能够以低功耗工作的半导体装置。

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