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1. 发明授权

US5483217A Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US5483217A
公开(公告)日：1996-01-09
申请号：US91718
申请日：1993-07-15
申请人： Takashi Nagasaka , Mitsuhiro Saitou , Takahisa Koyasu , Hiroyuki Ban , Yuji Otani , Kengo Oka , Kyoko Nagaoka
发明人： Takashi Nagasaka , Mitsuhiro Saitou , Takahisa Koyasu , Hiroyuki Ban , Yuji Otani , Kengo Oka , Kyoko Nagaoka
IPC分类号： H05K1/02 , H05K1/09 , H05K1/14 , H05K1/16 , H05K3/28 , H01C1/02
CPC分类号： H05K3/284 , H05K1/167 , H05K1/0271 , H05K1/095 , H05K1/141 , H05K2201/0317 , H05K2201/09236 , H05K2201/10386 , H05K2201/10545
摘要： An electronic circuit device decreases dispersion in the output of the circuit caused by changes in the resistance of the resistors resulting from stress. Resistor positions are selected on the circuit board so that a change in the circuit output caused by a change in resistance of a first resistor group becomes equal to a change caused by a change in resistance caused by a second resistor group, these changes being in opposite directions so as to cancel each other. Alternately, a plurality of resistors are connected to form a composite resistor such that the effect upon resistance of the composite resistor caused by the resistor having decreased resistance is cancelled by the effect upon resistance of the composite resistor caused by a resistor having an increased resistance.
摘要翻译：电子电路装置减少由于应力引起的电阻电阻变化引起的电路输出中的色散。在电路板上选择电阻器位置，使得由第一电阻器组的电阻变化引起的电路输出的变化等于由第二电阻器组造成的电阻变化引起的变化，这些变化是相反的方向相互抵消。或者，连接多个电阻器以形成复合电阻器，使得由具有降低的电阻的电阻器引起的复合电阻器的电阻的影响由于由具有增加的电阻的电阻器引起的复合电阻器的电阻的影响而被抵消。

2. 发明授权

US06034556A Sample-and-hold circuit including operational amplifier as an input circuit 失效
标题翻译：采样保持电路包括运算放大器作为输入电路
公开(公告)号：US06034556A
公开(公告)日：2000-03-07
申请号：US19363
申请日：1998-02-05
申请人： Takahisa Koyasu , Mitsuhiro Saitou , Hiroyuki Ban
发明人： Takahisa Koyasu , Mitsuhiro Saitou , Hiroyuki Ban
IPC分类号： G11C27/02 , H03F3/30 , H03F3/45
CPC分类号： H03F3/3071 , G11C27/026 , H03F3/45085 , H03F2203/45594 , H03F2203/45612 , H03F2203/45618 , H03F2203/45674 , H03F2203/45722
摘要： An operational amplifier charges a charge storage capacitor in response to an input signal supplied to a non-inverting input terminal. When a switching signal is low, NPN transistors disposed in an output open circuit are on. Therefore, output transistors disposed in a push-pull circuit are off and the output signal is cut off. Further, in this situation, the potential of a phase compensation capacitor is held because AC coupling of the phase compensation capacitor does not occur.
摘要翻译：响应于提供给非反相输入端的输入信号，运算放大器对电荷存储电容器充电。当开关信号为低电平时，设置在输出开路中的NPN晶体管导通。因此，设置在推挽电路中的输出晶体管截止，输出信号被切断。此外，在这种情况下，由于不发生相位补偿电容器的AC耦合，因此保持相位补偿电容器的电位。

3. 发明授权

US5917246A Semiconductor package with pocket for sealing material 失效
标题翻译：半导体封装带口袋密封材料
公开(公告)号：US5917246A
公开(公告)日：1999-06-29
申请号：US620580
申请日：1996-03-22
申请人： Hirokazu Kasuya , Kouji Numazaki , Takahisa Koyasu , Mitsuhiro Saitou
发明人： Hirokazu Kasuya , Kouji Numazaki , Takahisa Koyasu , Mitsuhiro Saitou
IPC分类号： H01L23/28 , H01L21/56 , H01L23/24 , H01L23/29 , H01L23/31 , H05K3/28 , H05K3/34
CPC分类号： H01L23/24 , H01L21/56 , H01L2224/45144 , H01L2224/48091 , H05K3/284 , H05K3/3405
摘要： A semiconductor package, which secures the protection of circuit elements from the external environment, is disclosed. A single in-line package (SIP) is constructed by fixingly sealing a hybrid integrated circuit component within a casing with epoxy resin. A sleeve is bonded on the surface of a ceramic substrate. The sleeve is formed with silicon rubber into a pocket shape so as to cover respective circuit elements of the hybrid integrated circuit component. In the sleeve is made an opening part. Silicon gel is poured into the sleeve as a fixingly sealing material and cured to seal the respective circuit elements. Terminals downwardly extends in parallel with each other from an end part of the ceramic substrate through an opening part of the casing.
摘要翻译：公开了一种确保电路元件与外部环境的保护的半导体封装。单个在线封装（SIP）是通过将环形树脂固定密封在壳体内的混合集成电路部件构成的。套筒结合在陶瓷基板的表面上。套筒由硅橡胶形成为袋形，以覆盖混合集成电路部件的各个电路元件。在袖子里打开了一部分。将硅胶作为固定密封材料倒入套筒中并固化以密封各个电路元件。端子从陶瓷基板的端部通过壳体的开口部向下平行地延伸。

4. 发明授权

US5629702A Analog to digital converter 失效
标题翻译：模数转换器
公开(公告)号：US5629702A
公开(公告)日：1997-05-13
申请号：US318546
申请日：1994-10-05
申请人： Takahisa Koyasu , Mitsuhiro Saitou
发明人： Takahisa Koyasu , Mitsuhiro Saitou
IPC分类号： H03M1/14 , H03M1/36 , H03M1/42 , H03M1/66
CPC分类号： H03M1/42
摘要： An analog to digital converter comprises: first to n.sup.th comparators, having a tandem structure, for comparing an input voltage signal with first to n.sup.th reference voltages and outputting first to n.sup.th bit outputs respectively, said n being a natural number more than one, said first comparator outputting a most significant bit of said first bit output; a first reference voltage generation circuit for generating said first reference voltage; second to n.sup.th reference voltage generation circuits for generating said second to n.sup.th reference voltages, p.sup.th reference voltages being generated in accordance with outputs of said first to (p-1).sup.th comparators, said p being a natural number and l
摘要翻译：一种模数转换器包括：具有串联结构的第一至第n比较器，用于将输入电压信号与第一至第n参考电压进行比较，并分别输出第一至第n位输出，所述n为多于一个的自然数，所述第一比较器输出所述第一位输出的最高有效位; 用于产生所述第一参考电压的第一参考电压产生电路; 用于产生所述第二至第n参考电压的第二至第n参考电压产生电路，根据所述第一至第（p-1）比较器的输出产生第p参考电压，所述p为自然数，l

5. 发明授权

US5554881A Constitution of an electrode arrangement in a semiconductor element 失效
标题翻译：半导体元件中的电极布置的结构
公开(公告)号：US5554881A
公开(公告)日：1996-09-10
申请号：US357492
申请日：1994-12-15
申请人： Takahisa Koyasu , Kouji Numazaki , Hirokazu Kasuya , Mitsuhiro Saitou , Kazuhisa Ikeda
发明人： Takahisa Koyasu , Kouji Numazaki , Hirokazu Kasuya , Mitsuhiro Saitou , Kazuhisa Ikeda
IPC分类号： H01L23/485 , H01L29/70
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/45124 , H01L2224/45144 , H01L2224/4823 , H01L2224/4912 , H01L2224/49171 , H01L24/45 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01021 , H01L2924/01023 , H01L2924/01033 , H01L2924/01068 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/19043
摘要： At least four electrodes are provided on the same surface of a discrete transistor. Among these electrodes, one electrode is set as a base electrode, an electrode neighboring the base electrode in the up-and-down direction is set as an emitter electrode and an electrode neighboring the base electrode in the right-and-left direction is set as a collector electrode. On the same surface, a base electrode is provided at a position which is neither in the up-and-down direction nor in the right-and-left direction with respect to the base electrode. When the discrete transistor having this type of electrode arrangement is mounted on a substrate, one of the base electrodes formed on the substrate is connected to a first wiring, the collector electrode is connected to a second wiring, and the emitter electrode is connected to a third wiring.
摘要翻译：在分立晶体管的同一表面上设置至少四个电极。在这些电极中，将一个电极设置为基极，将与上下方向的基极相邻的电极设定为发射电极，并且设定与左右方向的基极相邻的电极作为集电极。在相同的表面上，基极相对于基极设置在既不在上下方向也不在左右方向上的位置。当具有这种类型的电极布置的分立晶体管安装在基板上时，形成在基板上的一个基极连接到第一布线，集电极连接到第二布线，并且发射极连接到第三线。

6. 发明授权

US6104076A Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US6104076A
公开(公告)日：2000-08-15
申请号：US748896
申请日：1996-11-15
申请人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
发明人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
IPC分类号： H01L21/336 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/085 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0251 , H01L27/0623 , H01L27/085 , H01L29/063 , H01L29/1083 , H01L29/1095 , H01L29/66674 , H01L29/7395 , H01L29/7801 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

7. 发明授权

US5719522A Reference voltage generating circuit having reduced current consumption with varying loads 失效
标题翻译：参考电压发生电路具有随着负载变化而具有降低的电流消耗
公开(公告)号：US5719522A
公开(公告)日：1998-02-17
申请号：US814935
申请日：1997-03-12
申请人： Mitsuhiro Saitou , Hajime Ito , Kiyoshi Yamamoto , Hiroyuki Ban
发明人： Mitsuhiro Saitou , Hajime Ito , Kiyoshi Yamamoto , Hiroyuki Ban
IPC分类号： G05F3/30 , G05F3/22 , G06F1/26 , G11C5/14 , G05F1/10
CPC分类号： G05F3/222 , G11C5/147
摘要： A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.
摘要翻译：可变负载电流供给单元将恒定电压输出单元消耗的电流供给到其电源端子，并通过基准电压输出端子向负载电路供给要消耗的电流。恒定电压输出单元将电源端子的电位即基准电压输出端子的电位维持在固定电位。基极电位控制单元将可变负载电流供给单元中的基准电压输出端子上的电位的变化负反馈到射极跟随器晶体管的基极。以这种方式，当负载电流消耗的电流减小并且参考电压输出端子上的电位稍微增加时，可变负载电流供应单元提供的电流减小。

8. 发明授权

US06831331B2 Power MOS transistor for absorbing surge current 失效
标题翻译：功率MOS晶体管，用于吸收浪涌电流
公开(公告)号：US06831331B2
公开(公告)日：2004-12-14
申请号：US09945621
申请日：2001-09-05
申请人： Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
发明人： Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0251 , H01L27/0623 , H01L27/085 , H01L29/1087 , H01L29/66674 , H01L29/7395 , H01L29/7801 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.
摘要翻译：提供具有功率晶体管结构的半导体器件。功率晶体管结构包括独立地设置在半导体层的表面部分处的多个第一阱; 深部区域，其具有设置在所述第一阱之间的所述半导体层中的部分; 漏电极，连接到所述第一阱中的相应的漏极区; 源电极，其连接到第一阱中的各个源极区域和沟道阱区域，使得漏极电极或源极电极连接到感性负载; 以及连接构件，用于向深区域提供源极电位，其中当漏电极连接到感性负载时，连接构件可配置为连接到漏电极，并且当源电极连接到源电极时连接到源电极表示感性负载。

9. 发明授权

US6104078A Design for a semiconductor device having elements isolated by insulating regions 失效
标题翻译：设计具有通过绝缘区隔离的元件的半导体器件
公开(公告)号：US6104078A
公开(公告)日：2000-08-15
申请号：US941756
申请日：1997-09-30
申请人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
发明人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76264
摘要： A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.
摘要翻译：一种半导体器件，包括具有主表面的半导体衬底。绝缘膜形成在半导体衬底的主表面上。半导体层被放置在绝缘膜上。从半导体层的表面延伸到绝缘膜的侧绝缘区域将半导体层分成元件区域。元件区域通过侧绝缘区域和绝缘膜彼此隔离。半导体基板的电阻率为1.5欧姆·厘米或更低。将半导体衬底处的电压设定为给定电压。

10. 发明授权

US5739546A Semiconductor wafer 失效
标题翻译：半导体晶圆
公开(公告)号：US5739546A
公开(公告)日：1998-04-14
申请号：US666646
申请日：1996-06-18
申请人： Mitsuhiro Saitou , Kouji Numazaki , Hiroyuki Ban
发明人： Mitsuhiro Saitou , Kouji Numazaki , Hiroyuki Ban
IPC分类号： H01L21/66 , H01L21/822 , H01L23/528 , H01L23/58 , H01L27/02 , H01L27/04 , H01L27/10
CPC分类号： H01L22/32 , H01L23/5286 , H01L27/0218 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.
摘要翻译：具有相对宽的电源线和接地线的半导体晶片，并且还可以防止这些线之间的短路。多个集成电路形成区域已经形成集成电路，被布置在半导体晶片上。在硅衬底上形成氧化硅膜，在氧化硅膜上形成接地线导体。该接地线导体在划线上延伸。在氧化硅膜上沉积由氧化硅膜构成的层绝缘膜，其间插入有接地线导体，并且在该层绝缘膜上形成与该接地线导体重叠的电源线导体。电源线导体在划线上延伸。在集成电路形成区域中，电源焊盘和电源线导体电连接。接地焊盘和接地线导体也电连接。

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