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1. 发明申请

US20060236145A1 Contents reproduction device 审中-公开
标题翻译：内容再现设备
公开(公告)号：US20060236145A1
公开(公告)日：2006-10-19
申请号：US11214868
申请日：2005-08-31
申请人： Takafumi Yuasa , Yukio Fujii , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata , Masakazu Ehama
发明人： Takafumi Yuasa , Yukio Fujii , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata , Masakazu Ehama
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3265 , Y02D10/153
摘要： A contents reproduction device realizes reduction of power consumption by controlling power supply control according to the input contents. More specifically, in the contents reproduction device, the PSI analysis unit analyzes additional information in the inputted contents so as to check whether video contents are contained or the signal detection unit checks whether the inputted contents contain a video signal. According to the check result, the video information detection unit detects whether the inputted contents contain video information and outputs the detection result to the power control unit. When the inputted contents contain video information, the power control unit supplies power to the display. When no video information is contained, the power control unit stops power supply to the display and turns off power supply to the display.
摘要翻译：内容再现装置通过根据输入内容控制电源控制来实现功耗的降低。更具体地，在内容再现装置中，PSI分析单元分析输入的内容中的附加信息，以便检查视频内容是否包含，或者信号检测单元检查输入的内容是否包含视频信号。根据检查结果，视频信息检测单元检测输入的内容是否包含视频信息，并将检测结果输出到电源控制单元。当输入的内容包含视频信息时，电源控制单元向显示器供电。当没有包含视频信息时，电源控制单元停止对显示器的电力供应，并且关闭对显示器的电源。

2. 发明申请

US20050119870A1 Processor system with execution-reservable accelerator 审中-公开
标题翻译：具有可执行加速器的处理器系统
公开(公告)号：US20050119870A1
公开(公告)日：2005-06-02
申请号：US10982830
申请日：2004-11-08
申请人： Koji Hosogi , Yukio Fujii , Kazuhiko Tanaka , Hiroaki Nakata , Masakazu Ehama
发明人： Koji Hosogi , Yukio Fujii , Kazuhiko Tanaka , Hiroaki Nakata , Masakazu Ehama
IPC分类号： G06F12/08 , G06F9/38 , G06F9/50 , G06F15/78 , G06F17/50 , G06T1/20 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/50 , H04N19/503 , H04N19/61 , H04N19/625 , H04N19/91
CPC分类号： G06T1/20 , G06F9/5083 , G06F15/7864 , H04N19/42
摘要： A processor system capable of performing high-speed image processing is provided. The processor system includes a CPU and an accelerator. The CPU connected to the accelerator issues reservations of activation requests to said accelerator. The accelerator has an issued request number counter for counting the number of requests issued by the CPU and a processed request number counter for counting the number of processed requests. The accelerator can activate itself when a counter value of the issued request number counter is larger than a counter value of the processed request number counter.
摘要翻译：提供了能够执行高速图像处理的处理器系统。处理器系统包括CPU和加速器。连接到加速器的CPU发出对所述加速器的激活请求的保留。加速器具有发出的请求号码计数器，用于对CPU发出的请求数进行计数，以及处理的请求号计数器，用于计数处理的请求数。当所发出的请求号码计数器的计数器值大于处理后的请求号码计数器的计数器值时，加速器可以自动激活。

3. 发明申请

US20050162438A1 System including address generator and address generator 审中-公开
标题翻译：系统包括地址发生器和地址发生器
公开(公告)号：US20050162438A1
公开(公告)日：2005-07-28
申请号：US10984974
申请日：2004-11-10
申请人： Hiroaki Nakata , Yukio Fujii , Kazuhiko Tanaka , Koji Hosogi , Masakazu Ehama
发明人： Hiroaki Nakata , Yukio Fujii , Kazuhiko Tanaka , Koji Hosogi , Masakazu Ehama
IPC分类号： G06F12/02 , G06F9/345 , G06F12/06 , G06F13/28 , G09G3/20 , G09G5/37 , G09G5/39
CPC分类号： G06F9/345 , G09G3/20 , G09G2340/0407
摘要： There are provided a system including an address generator and its address generator, capable of generating an address needed for resolution conversion or the like of display data, by using an adder and counters without using a multiplier, which is disadvantageous as regards the mounting area and operation speed when mounting the address generator on an integrated circuit. A first portion for selecting a value from a plurality of values prepared to calculate the next address and adding the selected value, and a second portion for generating a signal to control selection of the value to be added are prepared. A plurality of counters are prepared in the second portion, and the value to be added is selected based on values in these counters. This address generator is incorporated in a DMA controller, memory access controller, display controller or the like, to implement resolution conversion or the like.
摘要翻译：提供了一种包括地址发生器及其地址生成器的系统，其能够通过使用加法器和计数器而不使用乘法器来生成显示数据的分辨率转换等所需的地址，这对于安装区域是不利的，并且将地址发生器安装在集成电路上时的运行速度。准备用于从准备计算下一地址并添加所选值的多个值中选择值的第一部分，以及用于生成用于控制要添加的值的选择的信号的第二部分。在第二部分准备多个计数器，并且基于这些计数器中的值来选择要添加的值。该地址生成器被并入DMA控制器，存储器访问控制器，显示控制器等中，以实现分辨率转换等。

4. 发明申请

US20120263233A1 DATA PROCESSING CIRCUIT 审中-公开
标题翻译：数据处理电路
公开(公告)号：US20120263233A1
公开(公告)日：2012-10-18
申请号：US13533570
申请日：2012-06-26
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

5. 发明申请

US20080294878A1 PROCESSOR SYSTEM AND EXCEPTION PROCESSING METHOD 审中-公开
标题翻译：处理器系统和异常处理方法
公开(公告)号：US20080294878A1
公开(公告)日：2008-11-27
申请号：US12101437
申请日：2008-04-11
申请人： Takafumi YUASA , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Fumitaka Izuhara , Kazushi Akie
发明人： Takafumi YUASA , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Fumitaka Izuhara , Kazushi Akie
IPC分类号： G06F9/38 , G06F9/302 , G06F9/312
CPC分类号： G06F11/0793 , G06F9/30054 , G06F9/3861 , G06F9/3885 , G06F9/4812 , G06F11/0721 , G06F2209/481
摘要： When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.
摘要翻译：当在处理器系统中的错误检测单元中检测到错误时，错误检测单元向中断控制单元输出错误信号，并且中断控制单元向程序计数器输出错误地址寄存器和控制信号的值控制单元，并将程序计数器的值重写为错误地址寄存器的值。通过这种方式，实现了通过错误中断的分支过程。在这种情况下，当检测到错误时，不执行在发生错误时保存程序计数器的值的处理，以及特定的存储寄存器和控制电路，用于恢复到发生错误时的地址未提供错误处理结束后的错误发生。

6. 发明授权

US08223838B2 Parallel processing circuit for intra-frame prediction 失效
标题翻译：用于帧内预测的并行处理电路
公开(公告)号：US08223838B2
公开(公告)日：2012-07-17
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

7. 发明申请

US20080031329A1 DATA PROCESSING CIRCUIT 失效
标题翻译：数据处理电路
公开(公告)号：US20080031329A1
公开(公告)日：2008-02-07
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

8. 发明申请

US20070294514A1 Picture Processing Engine and Picture Processing System 审中-公开
标题翻译：图片处理引擎和图片处理系统
公开(公告)号：US20070294514A1
公开(公告)日：2007-12-20
申请号：US11688894
申请日：2007-03-21
申请人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
发明人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： To provide a technique to reduce power consumption when carrying out image processing by processors. For the purpose of this, for example, a means for specifying a two-dimensional source register and destination register is provided in an operand of an instruction, and the processor includes a means which executes calculation using a plurality of source registers in a plurality of cycles and obtains a plurality of destinations. Moreover, in an instruction to obtain a destination using a plurality of source registers and consuming a plurality of cycles, a data rounding processing part is connected to a final stage of a pipeline. With such configurations, the power consumed when reading an instruction memory is reduced by reducing the access frequency to the instruction memory, for example.
摘要翻译：提供一种在进行处理器进行图像处理时降低功耗的技术。为此目的，例如，在指令的操作数中提供用于指定二维源寄存器和目标寄存器的装置，并且处理器包括使用多个源寄存器中的多个源寄存器执行计算的装置循环并获得多个目的地。此外，在使用多个源寄存器获取目的地并消耗多个周期的指令中，数据舍入处理部分连接到流水线的最后一级。通过这样的配置，例如通过减少对指令存储器的访问频率来减少读取指令存储器时消耗的功率。

9. 发明授权

US07177996B2 Arrangements having security protection 有权
标题翻译：有安全保护的安排
公开(公告)号：US07177996B2
公开(公告)日：2007-02-13
申请号：US10801834
申请日：2004-03-17
申请人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
发明人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
IPC分类号： G06F12/00
CPC分类号： G06F12/1441 , G06F12/1027 , G06F12/1425
摘要： Security threats are reduced by providing a TLB in a bus interface unit of a media processor whose contents can be updated only from inside the media processor. The TLB checks whether an address specified by an external access request falls within access-permitted areas registered in it. If it does, an access request from outside is passed on to an inside of the media processor; otherwise, it is rejected.
摘要翻译：通过在媒体处理器的总线接口单元中提供TLB来减少安全威胁，其媒体处理器的内容可以仅从媒体处理器内部更新。 TLB检查由外部访问请求指定的地址是否落在其中注册的访问允许区域内。如果是这样，则来自外部的访问请求被传递到媒体处理器的内部; 否则就被拒绝。

10. 发明申请

US20050005081A1 Security system 有权
标题翻译：保安系统
公开(公告)号：US20050005081A1
公开(公告)日：2005-01-06
申请号：US10801834
申请日：2004-03-17
申请人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
发明人： Masakazu Ehama , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata
IPC分类号： G06F12/14 , G06F12/08 , G06F12/10
CPC分类号： G06F12/1441 , G06F12/1027 , G06F12/1425
摘要： A processor connected to an external bus in a conventional configuration made it possible to access its internal registers and local memory through the external bus and to read or update their contents. This created potential security threats including confidential data such as cryptographic keys being stolen and a newly developed piece of software being copied. In a conventional media processor connected to an external bus all access requests from a device connected on the external bus are honored. Security threats are reduced by providing a TLB in the bus interface unit of the media processor whose contents can be updated only from inside the media processor. The TLB checks whether the address specified by an external access request falls within the access-permitted areas registered in it. If it does, the access request from outside is passed on to the inside of the media processor; otherwise, it is rejected.
摘要翻译：以常规配置连接到外部总线的处理器使得可以通过外部总线访问其内部寄存器和本地存储器并读取或更新其内容。这产生了潜在的安全威胁，包括机密数据，例如加密密钥被盗，以及新开发的软件被复制。在连接到外部总线的常规媒体处理器中，来自连接在外部总线上的设备的所有访问请求都被保证。通过在媒体处理器的总线接口单元中提供TLB来减少安全威胁，其内容只能从媒体处理器内部更新。 TLB检查由外部访问请求指定的地址是否落在其中注册的访问允许区域内。如果是，则来自外部的访问请求被传递到媒体处理器的内部; 否则就被拒绝。

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