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1. 发明申请

US20070294514A1 Picture Processing Engine and Picture Processing System 审中-公开
标题翻译：图片处理引擎和图片处理系统
公开(公告)号：US20070294514A1
公开(公告)日：2007-12-20
申请号：US11688894
申请日：2007-03-21
申请人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
发明人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： To provide a technique to reduce power consumption when carrying out image processing by processors. For the purpose of this, for example, a means for specifying a two-dimensional source register and destination register is provided in an operand of an instruction, and the processor includes a means which executes calculation using a plurality of source registers in a plurality of cycles and obtains a plurality of destinations. Moreover, in an instruction to obtain a destination using a plurality of source registers and consuming a plurality of cycles, a data rounding processing part is connected to a final stage of a pipeline. With such configurations, the power consumed when reading an instruction memory is reduced by reducing the access frequency to the instruction memory, for example.
摘要翻译：提供一种在进行处理器进行图像处理时降低功耗的技术。为此目的，例如，在指令的操作数中提供用于指定二维源寄存器和目标寄存器的装置，并且处理器包括使用多个源寄存器中的多个源寄存器执行计算的装置循环并获得多个目的地。此外，在使用多个源寄存器获取目的地并消耗多个周期的指令中，数据舍入处理部分连接到流水线的最后一级。通过这样的配置，例如通过减少对指令存储器的访问频率来减少读取指令存储器时消耗的功率。

2. 发明申请

US20120263233A1 DATA PROCESSING CIRCUIT 审中-公开
标题翻译：数据处理电路
公开(公告)号：US20120263233A1
公开(公告)日：2012-10-18
申请号：US13533570
申请日：2012-06-26
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

3. 发明授权

US08223838B2 Parallel processing circuit for intra-frame prediction 失效
标题翻译：用于帧内预测的并行处理电路
公开(公告)号：US08223838B2
公开(公告)日：2012-07-17
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

4. 发明申请

US20080031329A1 DATA PROCESSING CIRCUIT 失效
标题翻译：数据处理电路
公开(公告)号：US20080031329A1
公开(公告)日：2008-02-07
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

5. 发明授权

US08483279B2 Moving image parallel processor having deblocking filters 有权
标题翻译：具有去块滤波器的运动图像并行处理器
公开(公告)号：US08483279B2
公开(公告)日：2013-07-09
申请号：US12819394
申请日：2010-06-21
申请人： Yoshitaka Hiramatsu , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki , Takafumi Yuasa , Kenichi Iwata
发明人： Yoshitaka Hiramatsu , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki , Takafumi Yuasa , Kenichi Iwata
IPC分类号： H04N7/12
CPC分类号： H04N19/86 , H04N19/423 , H04N19/436
摘要： A moving image processor includes a first and a second moving image processing unit which are able to perform parallel operation, and a data transfer unit having a first buffer and a second buffer. The first moving image processing unit processes macroblocks MB00, - - - , of one row of one image sequentially, and the second moving image processing unit processes macroblocks MB10, - - - , of the next row sequentially. The first and the second moving image processors include a first and a second deblocking filters, respectively. Operation timing of the second filter is delayed by the processing time of two macroblocks, compared with operation timing of the first filter. The processing results of the first filter and the second filter are transferred to an external memory via the first buffer and the second buffer of the transfer unit.
摘要翻译：运动图像处理器包括能够执行并行操作的第一和第二运动图像处理单元，以及具有第一缓冲器和第二缓冲器的数据传送单元。第一运动图像处理单元顺序地处理一行一个图像的宏块MB00，...，并且第二运动图像处理单元依次处理下一行的宏块MB10， - - - 。第一和第二运动图像处理器分别包括第一和第二去块滤波器。与第一滤波器的操作定时相比，第二滤波器的操作定时被延迟两个宏块的处理时间。第一滤波器和第二滤波器的处理结果经由传送单元的第一缓冲器和第二缓冲器传送到外部存储器。

6. 发明申请

US20060236145A1 Contents reproduction device 审中-公开
标题翻译：内容再现设备
公开(公告)号：US20060236145A1
公开(公告)日：2006-10-19
申请号：US11214868
申请日：2005-08-31
申请人： Takafumi Yuasa , Yukio Fujii , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata , Masakazu Ehama
发明人： Takafumi Yuasa , Yukio Fujii , Kazuhiko Tanaka , Koji Hosogi , Hiroaki Nakata , Masakazu Ehama
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3265 , Y02D10/153
摘要： A contents reproduction device realizes reduction of power consumption by controlling power supply control according to the input contents. More specifically, in the contents reproduction device, the PSI analysis unit analyzes additional information in the inputted contents so as to check whether video contents are contained or the signal detection unit checks whether the inputted contents contain a video signal. According to the check result, the video information detection unit detects whether the inputted contents contain video information and outputs the detection result to the power control unit. When the inputted contents contain video information, the power control unit supplies power to the display. When no video information is contained, the power control unit stops power supply to the display and turns off power supply to the display.
摘要翻译：内容再现装置通过根据输入内容控制电源控制来实现功耗的降低。更具体地，在内容再现装置中，PSI分析单元分析输入的内容中的附加信息，以便检查视频内容是否包含，或者信号检测单元检查输入的内容是否包含视频信号。根据检查结果，视频信息检测单元检测输入的内容是否包含视频信息，并将检测结果输出到电源控制单元。当输入的内容包含视频信息时，电源控制单元向显示器供电。当没有包含视频信息时，电源控制单元停止对显示器的电力供应，并且关闭对显示器的电源。

7. 发明申请

US20110080308A1 VARIABLE LENGTH CODE DECODING DEVICE AND DECODING METHOD 失效
标题翻译：可变长度代码解码器和解码方法
公开(公告)号：US20110080308A1
公开(公告)日：2011-04-07
申请号：US12961017
申请日：2010-12-06
申请人： Hiroaki NAKATA , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki NAKATA , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
摘要翻译：一种用于解码可变长度码数据的可变长度码解码装置，包括：存储多个具有参考关系的解码处理表的表存储器; 以及解码控制单元，其根据解码数据依次选择解码处理表以控制对可变长度代码数据进行解码的处理，其中当参考解码处理表来执行可变长度代码数据的初始解码时，当参考解码处理表的其他部分时，使用比用于参考解码处理表的可变长度代码数据更长的比特长进行初始解码处理。

8. 发明授权

US07864082B2 Variable length code decoding device and decoding method 有权
标题翻译：可变长度码解码装置及解码方法
公开(公告)号：US07864082B2
公开(公告)日：2011-01-04
申请号：US12467556
申请日：2009-05-18
申请人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that is given a start address and an initial reference bit length of the table memory; and sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
摘要翻译：一种用于解码可变长度码数据的可变长度码解码装置，包括：存储多个具有参考关系的解码处理表的表存储器; 以及解码控制单元，其被给予所述表存储器的起始地址和初始参考位长度; 并根据解码数据依次选择解码处理表，以控制对可变长度代码数据进行解码的处理，其中当参考解码处理表执行可变长度代码数据的初始解码时，进行初始解码处理通过比参考解码处理表的其他部分使用的比特长度从参考解码处理表的可变长度代码数据中减去更长的比特长度。

9. 发明申请

US20080212683A1 Image Decoding Device, Image Encoding Device and System LSI 审中-公开
标题翻译：图像解码装置，图像编码装置和系统LSI
公开(公告)号：US20080212683A1
公开(公告)日：2008-09-04
申请号：US11939807
申请日：2007-11-14
申请人： Hiroaki Nakata , Takafumi Yuasa , Fumitaka Izuhara , Kazushi Akie
发明人： Hiroaki Nakata , Takafumi Yuasa , Fumitaka Izuhara , Kazushi Akie
IPC分类号： G06K9/36
CPC分类号： H04N19/436 , H04N19/12 , H04N19/13 , H04N19/44 , H04N19/70
摘要： An image decoding device according to the present invention is an image decoding device responding to decoding of an image encoding method selecting an encoding table and an encoding format to use according to the kind of a parameter included in encoded data and comprises a bit stream processing unit converting a bit stream of the encoded data into an intermediate format and an image processing unit decoding data converted into the intermediate format and converting the same into image data. The bit stream processing unit and the image processing unit start independently. An image encoding device according to the present invention, in the same manner, comprises an image processing unit converting image data to be encoded into an intermediate format and a bit stream processing unit encoding the data converted into the intermediate format and converting the same into a bit stream. Thereby, image encoding and decoding processings with a low operation frequency and low power consumption is realized.
摘要翻译：根据本发明的图像解码装置是响应于根据编码数据中包括的参数的种类选择编码表和编码格式的图像编码方法的解码的图像解码装置，并且包括位流处理单元将编码数据的比特流转换为中间格式，以及图像处理单元，将转换成中间格式的数据解码并转换为图像数据。位流处理单元和图像处理单元独立地起动。根据本发明的图像编码装置以相同的方式，包括将要编码的图像数据转换为中间格式的图像处理单元和将转换成中间格式的数据编码为比特流处理单元，并将其转换为位流。从而，实现了低操作频率和低功耗的图像编码和解码处理。

10. 发明授权

US08884792B2 Variable length code decoding device and decoding method 有权
标题翻译：可变长度码解码装置及解码方法
公开(公告)号：US08884792B2
公开(公告)日：2014-11-11
申请号：US13602360
申请日：2012-09-04
申请人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40 , H03M7/42 , H04N19/176 , H03M7/30 , H04N19/61 , H03M7/46
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.
摘要翻译：可变长度码解码装置，用于解码可变长度码数据，包括：解码处理表，每个包括至少两种格式，包括第一格式，第一格式存储用于指定随后的解码过程中要参考的后续表的标识信息;以及第二格式，其存储通过重复解码处理而获得的解码值以及关于可变长度代码数据参考的有效位长度。该设备利用第一，第二，第三和第四格式和相对地址。

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