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1. 发明申请

US20070294514A1 Picture Processing Engine and Picture Processing System 审中-公开
标题翻译：图片处理引擎和图片处理系统
公开(公告)号：US20070294514A1
公开(公告)日：2007-12-20
申请号：US11688894
申请日：2007-03-21
申请人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
发明人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： To provide a technique to reduce power consumption when carrying out image processing by processors. For the purpose of this, for example, a means for specifying a two-dimensional source register and destination register is provided in an operand of an instruction, and the processor includes a means which executes calculation using a plurality of source registers in a plurality of cycles and obtains a plurality of destinations. Moreover, in an instruction to obtain a destination using a plurality of source registers and consuming a plurality of cycles, a data rounding processing part is connected to a final stage of a pipeline. With such configurations, the power consumed when reading an instruction memory is reduced by reducing the access frequency to the instruction memory, for example.
摘要翻译：提供一种在进行处理器进行图像处理时降低功耗的技术。为此目的，例如，在指令的操作数中提供用于指定二维源寄存器和目标寄存器的装置，并且处理器包括使用多个源寄存器中的多个源寄存器执行计算的装置循环并获得多个目的地。此外，在使用多个源寄存器获取目的地并消耗多个周期的指令中，数据舍入处理部分连接到流水线的最后一级。通过这样的配置，例如通过减少对指令存储器的访问频率来减少读取指令存储器时消耗的功率。

2. 发明申请

US20120263233A1 DATA PROCESSING CIRCUIT 审中-公开
标题翻译：数据处理电路
公开(公告)号：US20120263233A1
公开(公告)日：2012-10-18
申请号：US13533570
申请日：2012-06-26
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

3. 发明授权

US08223838B2 Parallel processing circuit for intra-frame prediction 失效
标题翻译：用于帧内预测的并行处理电路
公开(公告)号：US08223838B2
公开(公告)日：2012-07-17
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

4. 发明申请

US20080031329A1 DATA PROCESSING CIRCUIT 失效
标题翻译：数据处理电路
公开(公告)号：US20080031329A1
公开(公告)日：2008-02-07
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

5. 发明授权

US08483279B2 Moving image parallel processor having deblocking filters 有权
标题翻译：具有去块滤波器的运动图像并行处理器
公开(公告)号：US08483279B2
公开(公告)日：2013-07-09
申请号：US12819394
申请日：2010-06-21
申请人： Yoshitaka Hiramatsu , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki , Takafumi Yuasa , Kenichi Iwata
发明人： Yoshitaka Hiramatsu , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki , Takafumi Yuasa , Kenichi Iwata
IPC分类号： H04N7/12
CPC分类号： H04N19/86 , H04N19/423 , H04N19/436
摘要： A moving image processor includes a first and a second moving image processing unit which are able to perform parallel operation, and a data transfer unit having a first buffer and a second buffer. The first moving image processing unit processes macroblocks MB00, - - - , of one row of one image sequentially, and the second moving image processing unit processes macroblocks MB10, - - - , of the next row sequentially. The first and the second moving image processors include a first and a second deblocking filters, respectively. Operation timing of the second filter is delayed by the processing time of two macroblocks, compared with operation timing of the first filter. The processing results of the first filter and the second filter are transferred to an external memory via the first buffer and the second buffer of the transfer unit.
摘要翻译：运动图像处理器包括能够执行并行操作的第一和第二运动图像处理单元，以及具有第一缓冲器和第二缓冲器的数据传送单元。第一运动图像处理单元顺序地处理一行一个图像的宏块MB00，...，并且第二运动图像处理单元依次处理下一行的宏块MB10， - - - 。第一和第二运动图像处理器分别包括第一和第二去块滤波器。与第一滤波器的操作定时相比，第二滤波器的操作定时被延迟两个宏块的处理时间。第一滤波器和第二滤波器的处理结果经由传送单元的第一缓冲器和第二缓冲器传送到外部存储器。

6. 发明申请

US20090013152A1 COMPUTING UNIT AND IMAGE FILTERING DEVICE 审中-公开
标题翻译：计算单元和图像滤波器件
公开(公告)号：US20090013152A1
公开(公告)日：2009-01-08
申请号：US12168416
申请日：2008-07-07
申请人： Masakazu EHAMA , Koji Hosogi , Seiji Mochizuki
发明人： Masakazu EHAMA , Koji Hosogi , Seiji Mochizuki
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06T1/20 , G06T7/223 , G06T2207/10016 , G06T2207/20021
摘要： A processor capable of performing a filter processing in a high speed is provided. A computing unit comprises a computer for performing a filter processing. Data supply to the computer is performed by an internal register configured by a flip-flop. Data read from the internal register is outputted to a shift register and the data is supplied to the computer per cycle. And, the computing unit comprises a mechanism for changing a filter computing direction according to a motion vector, thereby preventing performance lowering due to branched command by performing a horizontal filtering and a vertical filtering by a same command.
摘要翻译：提供能够高速进行滤波处理的处理器。计算单元包括用于执行滤波处理的计算机。通过由触发器配置的内部寄存器来执行向计算机提供的数据。从内部寄存器读取的数据被输出到移位寄存器，并且每个周期将数据提供给计算机。并且，计算单元包括用于根据运动矢量改变滤波器计算方向的机构，从而通过执行水平滤波和通过相同命令的垂直滤波来防止由分支命令引起的性能降低。

7. 发明申请

US20100211623A1 FILTER PROCESSING MODULE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：过滤处理模块和半导体器件
公开(公告)号：US20100211623A1
公开(公告)日：2010-08-19
申请号：US12705898
申请日：2010-02-15
申请人： Yoshitaka HIRAMATSU , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki
发明人： Yoshitaka HIRAMATSU , Hiroaki Nakata , Masakazu Ehama , Seiji Mochizuki
IPC分类号： G06F17/10 , G06F5/01
CPC分类号： G06F17/153 , G06T1/20 , H03H17/0202
摘要： The present invention is directed to improve efficiency of a filter processing on an image. A filter processing module includes a filter circuit and a control circuit. The filter circuit includes: a first register capable of storing data; a first arithmetic logic unit capable of executing a first filter processing on the basis of output data of the first register; a second register capable of storing a result of the arithmetic operation of the first arithmetic logic unit; and a second arithmetic logic unit capable of executing a second filter processing on the basis of output data of the second register. The control circuit adjusts the number of pieces of data which is input per cycle in the first register in accordance with the number of taps in the first filter processing, size of an execution result of the first filter processing, and the number of second arithmetic logic units, thereby promptly completing the first filter processing.
摘要翻译：本发明旨在提高对图像的滤波处理的效率。滤波器处理模块包括滤波电路和控制电路。滤波电路包括：能够存储数据的第一寄存器; 第一算术逻辑单元，其能够基于第一寄存器的输出数据执行第一滤波处理; 第二寄存器，其能够存储第一算术逻辑单元的算术运算结果; 以及能够基于第二寄存器的输出数据执行第二滤波处理的第二算术逻辑单元。控制电路根据第一滤波处理中的抽头数，第一滤波处理的执行结果的大小和第二算术逻辑的数量来调整在第一寄存器中每个周期输入的数据数单位，从而及时完成第一次过滤处理。

8. 发明申请

US20120294373A1 MOVING IMAGE ENCODING METHOD, MOVING IMAGE DECODING METHOD, MOVING IMAGE ENCODING DEVICE, AND MOVING IMAGE DECODING DEVICE 审中-公开
标题翻译：移动图像编码方法，移动图像解码方法，移动图像编码装置和移动图像解码装置
公开(公告)号：US20120294373A1
公开(公告)日：2012-11-22
申请号：US13519874
申请日：2010-12-14
申请人： Seiji Mochizuki , Kazushi Akie , Tetsuya Shibayama , Kenichi Iwata
发明人： Seiji Mochizuki , Kazushi Akie , Tetsuya Shibayama , Kenichi Iwata
IPC分类号： H04N7/32
CPC分类号： H04N19/85 , H04N19/129 , H04N19/176 , H04N19/423 , H04N19/436
摘要： The moving image encoding method includes encoding macro-blocks included in a landscape picture frame of a moving image having a larger horizontal width in a horizontal direction than a vertical width in a vertical direction by an encoding device. In macro-block encoding, information of the encoded macro-blocks surrounding a macro-block to be encoded is stored in a built-in information storing memory of the encoding device. Further, in the encoding, first a vertical array of macro-blocks at the left end of the horizontal width of the landscape picture frame are encoded sequentially, and the resultant encode information is stored in the information storing memory, and subsequently an adjacent vertical array of the plural macro-blocks located horizontally on the right of the left end of the horizontal width of the landscape picture frame are encoded sequentially.
摘要翻译：运动图像编码方法包括通过编码装置对包括在水平方向上的水平宽度比垂直方向上的垂直宽度的运动图像的景观图像帧中的宏块进行编码。在宏块编码中，将要编码的宏块周围的编码宏块的信息存储在编码装置的内置信息存储存储器中。此外，在编码中，首先对横向图像帧的水平宽度的左端的宏块的垂直阵列进行顺序编码，并将所得到的编码信息存储在信息存储存储器中，随后将相邻的垂直阵列水平位于横向画面帧的水平宽度的左端右侧的多个宏块的顺序编码。

9. 发明申请

US20120275771A1 DATA PROCESSING DEVICE, IMAGE ENCODING/DECODING DEVICE AND DATA PROCESSING SYSTEM 有权
标题翻译：数据处理设备，图像编码/解码设备和数据处理系统
公开(公告)号：US20120275771A1
公开(公告)日：2012-11-01
申请号：US13469182
申请日：2012-05-11
申请人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
发明人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
IPC分类号： H04N5/92
CPC分类号： H04N19/12 , G06F9/50 , H04N19/436
摘要： An image encoding/decoding device includes a first circuit and a second circuit for providing initial setting to image processing modules. The image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from an external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to an image processing module according to the setting-target information. The CPU does not need to set the whole information, which is initially set to the image processing modules, directly to the image encoding/decoding device, and also does not need to set both a transfer source address and a transfer destination address as in DMA transfer.
摘要翻译：图像编码/解码装置包括用于向图像处理模块提供初始设置的第一电路和第二电路。图像编码/解码装置不直接从外部CPU接收最初设置到图像处理模块的信息，并且从CPU向第一电路设置用于初始设置的控制信息。第二电路使用在第一电路中设置的控制信息从外部读入初始设置信息和初始设置信息的设置目标信息，并根据设置目标信息将初始设置信息传送到图像处理模块。 CPU不需要将初始设置为图像处理模块的整个信息直接设置到图像编码/解码设备，也不需要像DMA那样设置传输源地址和传输目标地址转让。

10. 发明授权

US08189935B2 Data processing device, image encoding/decoding device and data processing system 失效
标题翻译：数据处理装置，图像编解码装置及数据处理系统
公开(公告)号：US08189935B2
公开(公告)日：2012-05-29
申请号：US12399956
申请日：2009-03-08
申请人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
发明人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
IPC分类号： G06K9/36
CPC分类号： H04N19/12 , G06F9/50 , H04N19/436
摘要： To reduce a processing load of an external CPU, when a large amount of data is initially set frequently to an image coding/decoding device. The image encoding/decoding device (data processing device) includes a first circuit and a second circuit for providing initial setting to a plurality of image processing modules (processor units), wherein the image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from the external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to the image processing module according to the read-in setting-target information.
摘要翻译：为了减少外部CPU的处理负担，当大量的数据最初被频繁地设置到图像编码/解码装置时。图像编码/解码装置（数据处理装置）包括第一电路和第二电路，用于向多个图像处理模块（处理器单元）提供初始设置，其中图像编码/解码装置不接收最初的信息设置为图像处理模块，直接从外部CPU，初始设置的控制信息设置为CPU的第一个电路。第二电路使用在第一电路中设置的控制信息从外部读入初始设置信息和初始设置信息的设置目标信息，并根据读入设置目标信息将初始设置信息传送到图像处理模块。

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