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1. 发明申请

US20070294514A1 Picture Processing Engine and Picture Processing System 审中-公开
标题翻译：图片处理引擎和图片处理系统
公开(公告)号：US20070294514A1
公开(公告)日：2007-12-20
申请号：US11688894
申请日：2007-03-21
申请人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
发明人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： To provide a technique to reduce power consumption when carrying out image processing by processors. For the purpose of this, for example, a means for specifying a two-dimensional source register and destination register is provided in an operand of an instruction, and the processor includes a means which executes calculation using a plurality of source registers in a plurality of cycles and obtains a plurality of destinations. Moreover, in an instruction to obtain a destination using a plurality of source registers and consuming a plurality of cycles, a data rounding processing part is connected to a final stage of a pipeline. With such configurations, the power consumed when reading an instruction memory is reduced by reducing the access frequency to the instruction memory, for example.
摘要翻译：提供一种在进行处理器进行图像处理时降低功耗的技术。为此目的，例如，在指令的操作数中提供用于指定二维源寄存器和目标寄存器的装置，并且处理器包括使用多个源寄存器中的多个源寄存器执行计算的装置循环并获得多个目的地。此外，在使用多个源寄存器获取目的地并消耗多个周期的指令中，数据舍入处理部分连接到流水线的最后一级。通过这样的配置，例如通过减少对指令存储器的访问频率来减少读取指令存储器时消耗的功率。

2. 发明申请

US20120263233A1 DATA PROCESSING CIRCUIT 审中-公开
标题翻译：数据处理电路
公开(公告)号：US20120263233A1
公开(公告)日：2012-10-18
申请号：US13533570
申请日：2012-06-26
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

3. 发明授权

US08223838B2 Parallel processing circuit for intra-frame prediction 失效
标题翻译：用于帧内预测的并行处理电路
公开(公告)号：US08223838B2
公开(公告)日：2012-07-17
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

4. 发明申请

US20080031329A1 DATA PROCESSING CIRCUIT 失效
标题翻译：数据处理电路
公开(公告)号：US20080031329A1
公开(公告)日：2008-02-07
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

5. 发明授权

US08189935B2 Data processing device, image encoding/decoding device and data processing system 失效
标题翻译：数据处理装置，图像编解码装置及数据处理系统
公开(公告)号：US08189935B2
公开(公告)日：2012-05-29
申请号：US12399956
申请日：2009-03-08
申请人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
发明人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
IPC分类号： G06K9/36
CPC分类号： H04N19/12 , G06F9/50 , H04N19/436
摘要： To reduce a processing load of an external CPU, when a large amount of data is initially set frequently to an image coding/decoding device. The image encoding/decoding device (data processing device) includes a first circuit and a second circuit for providing initial setting to a plurality of image processing modules (processor units), wherein the image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from the external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to the image processing module according to the read-in setting-target information.
摘要翻译：为了减少外部CPU的处理负担，当大量的数据最初被频繁地设置到图像编码/解码装置时。图像编码/解码装置（数据处理装置）包括第一电路和第二电路，用于向多个图像处理模块（处理器单元）提供初始设置，其中图像编码/解码装置不接收最初的信息设置为图像处理模块，直接从外部CPU，初始设置的控制信息设置为CPU的第一个电路。第二电路使用在第一电路中设置的控制信息从外部读入初始设置信息和初始设置信息的设置目标信息，并根据读入设置目标信息将初始设置信息传送到图像处理模块。

6. 发明授权

US08467618B2 Data processing device, image encoding/decoding device and data processing system 有权
标题翻译：数据处理装置，图像编解码装置及数据处理系统
公开(公告)号：US08467618B2
公开(公告)日：2013-06-18
申请号：US13469182
申请日：2012-05-11
申请人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
发明人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
IPC分类号： H04N7/50
CPC分类号： H04N19/12 , G06F9/50 , H04N19/436
摘要： An image encoding/decoding device includes a first circuit and a second circuit for providing initial setting to image processing modules. The image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from an external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to an image processing module according to the setting-target information. The CPU does not need to set the whole information, which is initially set to the image processing modules, directly to the image encoding/decoding device, and also does not need to set both a transfer source address and a transfer destination address as in DMA transfer.
摘要翻译：图像编码/解码装置包括用于向图像处理模块提供初始设置的第一电路和第二电路。图像编码/解码装置不直接从外部CPU接收最初设置到图像处理模块的信息，并且从CPU向第一电路设置用于初始设置的控制信息。第二电路使用在第一电路中设置的控制信息从外部读入初始设置信息和初始设置信息的设置目标信息，并根据设置目标信息将初始设置信息传送到图像处理模块。 CPU不需要将初始设置为图像处理模块的整个信息直接设置到图像编码/解码设备，也不需要像DMA那样设置传输源地址和传输目标地址转让。

7. 发明申请

US20120275771A1 DATA PROCESSING DEVICE, IMAGE ENCODING/DECODING DEVICE AND DATA PROCESSING SYSTEM 有权
标题翻译：数据处理设备，图像编码/解码设备和数据处理系统
公开(公告)号：US20120275771A1
公开(公告)日：2012-11-01
申请号：US13469182
申请日：2012-05-11
申请人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
发明人： Hiroshi Ueda , Kenichi Iwata , Seiji Mochizuki
IPC分类号： H04N5/92
CPC分类号： H04N19/12 , G06F9/50 , H04N19/436
摘要： An image encoding/decoding device includes a first circuit and a second circuit for providing initial setting to image processing modules. The image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from an external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to an image processing module according to the setting-target information. The CPU does not need to set the whole information, which is initially set to the image processing modules, directly to the image encoding/decoding device, and also does not need to set both a transfer source address and a transfer destination address as in DMA transfer.
摘要翻译：图像编码/解码装置包括用于向图像处理模块提供初始设置的第一电路和第二电路。图像编码/解码装置不直接从外部CPU接收最初设置到图像处理模块的信息，并且从CPU向第一电路设置用于初始设置的控制信息。第二电路使用在第一电路中设置的控制信息从外部读入初始设置信息和初始设置信息的设置目标信息，并根据设置目标信息将初始设置信息传送到图像处理模块。 CPU不需要将初始设置为图像处理模块的整个信息直接设置到图像编码/解码设备，也不需要像DMA那样设置传输源地址和传输目标地址转让。

8. 发明授权

US09023835B2 Agent for ameliorating blood-brain barrier disorders 有权
标题翻译：改善血脑屏障障碍的药剂
公开(公告)号：US09023835B2
公开(公告)日：2015-05-05
申请号：US13390058
申请日：2010-08-09
申请人： Hiroshi Ueda
发明人： Hiroshi Ueda
IPC分类号： A61K38/22 , A61K45/06
CPC分类号： A61K38/2292 , A61K45/06 , A61K2300/00
摘要： The invention provides a method of ameliorating a blood-brain barrier disorder, as well as a method of treating a disease accompanied by a blood-brain barrier disorder and a method of treating a cerebral ischemic disease, by administering a prothymosin α, or a protein or polypeptide possessing the same function as the prothymosin α. The invention also provides polypeptides useful in the context of the aforesaid methods.
摘要翻译：本发明提供一种改善血脑屏障障碍的方法，以及治疗伴有血脑屏障障碍的疾病的方法和治疗脑缺血疾病的方法，通过施用孕激素α或蛋白质或具有与胸腺素α相同功能的多肽。本发明还提供了在上述方法的上下文中有用的多肽。

9. 发明申请

US20130203738A1 USE OF COMPOUND BINDING TO MSIN3B THAT SPECIFICALLY BINDS TO NEURON RESTRICTIVE SILENCER FACTOR (NRSF) 有权
标题翻译：使用化合物结合到MSIN3B，特异性结合到神经元限制性沉默因子（NRSF）
公开(公告)号：US20130203738A1
公开(公告)日：2013-08-08
申请号：US13578230
申请日：2011-02-09
申请人： Yoshifumi Nishimura , Aritaka Nagadoi , Yuuka Hirao , Yoshio Goshima , Naoya Yamashita , Naoki Miyata , Takayoshi Suzuki , Ryuta Hiraishi , Hiroshi Ueda
发明人： Yoshifumi Nishimura , Aritaka Nagadoi , Yuuka Hirao , Yoshio Goshima , Naoya Yamashita , Naoki Miyata , Takayoshi Suzuki , Ryuta Hiraishi , Hiroshi Ueda
IPC分类号： C07D211/16 , C07D211/10 , C07D265/30 , C07D207/06 , C07D223/04 , C07D225/02 , C07D211/14 , C07C233/65
CPC分类号： C07D211/16 , A61K31/445 , C07C233/65 , C07C233/66 , C07C2601/14 , C07D207/06 , C07D211/10 , C07D211/14 , C07D211/96 , C07D223/04 , C07D225/02 , C07D265/30 , C07D295/192
摘要： The present invention identifies a compound which binds to the PAH1 domain of mSin3B that specifically binds to neural restrictive silencer factor NRSF, and uses the compound as a prophylactic and/or a therapeutic for diseases associated with abnormal expression of neural restrictive silencer factor NRSF/REST or abnormal expression of genes targeted by NRSF/REST, such as Huntington's disease, medulloblastoma and neuropathic pain.The present invention provides a pharmaceutical composition comprising a substance capable of binding to the PAH1 domain of mSin3B, e.g., a compound represented by the following formula (I), a pharmacologically acceptable salt thereof, or a pharmacologically acceptable ester thereof: wherein n represents 0 or 1; R1, R2, R3, R4 and R5 each independently represent a hydrogen atom, a hydrocarbon group or a functional group; Y represents a single bond, a carbonyl group, —CONH—, —NHCO— or a sulfonyl group; and Z represents a nitrogen-containing heterocyclic group which may have a substituent, an amino group which may have a hydrocarbon group or an aromatic hydrocarbon group, or a nitrogen and oxygen-containing heterocyclic group which may have a substituent.
摘要翻译：本发明鉴定了与特异性结合神经限制性沉默因子NRSF的mSin3B的PAH1结构域结合的化合物，并且将该化合物用作与神经限制性消音因子NRSF / REST的异常表达相关的疾病的预防和/或治疗或NRSF / REST靶向的基因异常表达，如亨廷顿氏病，成神经管细胞瘤和神经性疼痛。本发明提供一种药物组合物，其包含能够结合mSin3B的PAH1结构域的物质，例如下式（I）表示的化合物，其药理学上可接受的盐或其药理学上可接受的酯：其中n表示0 或1; R1，R2，R3，R4和R5各自独立地表示氢原子，烃基或官能团; Y表示单键，羰基，-CONH-，-NHCO-或磺酰基; Z表示可以具有取代基的含氮杂环基，可以具有烃基或芳香族烃基的氨基或可以具有取代基的含氮和含氧杂环基。

10. 发明授权

US08411196B2 Digital camera with movable mirror for AF in live view mode and optical viewfinder mode 有权
标题翻译：带实时取景模式和光学取景器模式的AF的可移动镜头的数码相机
公开(公告)号：US08411196B2
公开(公告)日：2013-04-02
申请号：US12095818
申请日：2006-11-30
申请人： Hiroshi Ueda , Kenichi Honjo , Naoto Yumiki , Toshio Makabe , Kenji Maeda , Kaoru Mokunaka , Kazuhiko Ishimaru
发明人： Hiroshi Ueda , Kenichi Honjo , Naoto Yumiki , Toshio Makabe , Kenji Maeda , Kaoru Mokunaka , Kazuhiko Ishimaru
IPC分类号： H04N5/232
CPC分类号： H04N5/23203 , G03B19/00 , G03B19/12 , H04N5/2254 , H04N5/23212 , H04N5/23245 , H04N5/23293 , H04N5/238
摘要： A digital camera of the present invention includes a microcomputer 110 having a live view mode controlling so that image data generated by a CMOS sensor 130 or image data obtained by subjecting the image data generated by the CMOS sensor 130 to predetermined processing is displayed on a liquid crystal monitor 150 as a moving image in real time, wherein when a release button 141 receives an instruction regarding start of an autofocus operation in a live view mode, the microcomputer 110 controls a movable mirror to enter an optical path to measure by an AF sensor 132, and thereafter, allow the movable mirror to retract from the optical path to return the digital camera to the live view mode. Due to this configuration, in a digital camera that includes a movable mirror and is capable of displaying a subject image in a live view through an electronic viewfinder, the operability thereof can be enhanced.
摘要翻译：本发明的数码相机包括具有实时取景模式控制的微型计算机110，使得由CMOS传感器130生成的图像数据或通过对由CMOS传感器130生成的图像数据进行预定处理而获得的图像数据显示在液体晶体监视器150作为运动图像实时地实现，其中当释放按钮141接收到关于在实时取景模式中的自动对焦操作的开始的指令时，微型计算机110控制可移动反射镜进入光学路径以由AF传感器 132，然后允许可移动镜从光路缩回以将数字照相机返回到实时取景模式。由于这种结构，在包括可移动镜并且能够通过电子取景器在实时取景中显示被摄体图像的数码相机中，可以提高其可操作性。

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