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1. 发明授权

US5729702A Multi-level round robin arbitration system 失效
标题翻译：多级循环仲裁系统
公开(公告)号：US5729702A
公开(公告)日：1998-03-17
申请号：US772782
申请日：1996-12-24
申请人： Tadhg Creedon , Richard A. Gahan , Fearghal Morgan
发明人： Tadhg Creedon , Richard A. Gahan , Fearghal Morgan
IPC分类号： G06F13/364 , G06F13/14 , G06F13/37
CPC分类号： G06F13/364
摘要： Arbitration means for arbitrating between computer devices A to F which compete for access to a common bus. The system provides cascaded round-robin units. Unit RR1 has ports A, B, C, and X in sequence, with port X coupled to round-robin unit RR2, which has ports D, E, F in sequence. On each cycling of unit RR1 past C to A, unit RR2 is checked and the next one of devices D to F (in the sequence determined by unit RR2) has the opportunity of bus access. A gating circuit 13 can further restrict bus accessing by unit RR2's devices, by timing or counter control. A third round-robin unit can be added coupled to unit RR1 (which would have ports A, B, C, X,Y) or to unit RR2 (which would have ports D, E, F, Y). The assignment of devices to ports can be controllable by a matrix switch and device assignment memory.
摘要翻译：仲裁意味着在计算机设备A到F之间进行仲裁，竞争访问公共总线。该系统提供级联循环单元。单元RR1依次具有端口A，B，C和X，端口X与循环单元RR2相连，其具有端口D，E，F。在单元RR1经过C到A的每个循环之后，检查单元RR2，并且设备D到F中的下一个（由单元RR2确定的顺序）具有总线访问的机会。选通电路13可以通过定时或反向控制来进一步限制通过单元RR2的设备的总线访问。可以将第三循环单元添加到单元RR1（其将具有端口A，B，C，X，Y）或单元RR2（其将具有端口D，E，F，Y）。设备到端口的分配可以通过矩阵开关和设备分配存储器来控制。

2. 发明授权

US09158727B2 Addressable integrated circuit and method thereof 有权
标题翻译：可寻址集成电路及其方法
公开(公告)号：US09158727B2
公开(公告)日：2015-10-13
申请号：US12771302
申请日：2010-04-30
申请人： Jeremy Gorbold , James Gibbons , Tadhg Creedon , Katherine O'Riordan , John Reidy , John Morrissey
发明人： Jeremy Gorbold , James Gibbons , Tadhg Creedon , Katherine O'Riordan , John Reidy , John Morrissey
IPC分类号： G01R19/175 , G01R19/14 , G06F3/00 , G06F3/01 , G06F13/42 , G06F12/06 , G01R31/36
CPC分类号： G06F13/4247 , G01R31/3658 , G06F12/0661
摘要： An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.
摘要翻译：在菊花链网络中寻址集成电路的示例性方法和系统。在示例性方法中，可以将集成电路的地址初始化为预定的初始地址。集成电路可以接收包括类型标识符和地址字段的命令。基于类型标识符，可以确定命令的类型。作为决定的结果，从地址字段读取地址。读取地址可以存储在寄存器中。该地址可以被修改，并且可以被输出。在接收到数据或命令时，可以通过错误检查算法来确认包括接收到的命令中的数据的数据的完整性。

3. 发明授权

US5241632A Programmable priority arbiter 失效
标题翻译：可编程优先仲裁器
公开(公告)号：US5241632A
公开(公告)日：1993-08-31
申请号：US828026
申请日：1992-01-30
申请人： Anne O'Connell , Tadhg Creedon , Deidre A. Smith
发明人： Anne O'Connell , Tadhg Creedon , Deidre A. Smith
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： The present invention is directed to a programmable logic circuit used as an arbiter to control access to a shared resource, e.g. a system bus, by N devices in a computer system. The programmable arbiter according to the present invention, implements a logic design with sufficient flexibility to accommodate and selectively incorporate features of several different arbitration schemes including a straight priority scheme, a programmable arbitration, and a rotating priority arbitration scheme. In addition to these arbitration schemes, the arbiter of the present invention supports an extended programmable arbitration scheme whereby a device which is requesting access to the shared resource may be granted access to the resource even if it has used up its allocated share of bandwidth if there are no other devices requesting access to the shared resource. Furthermore, bus bandwidth may be allocated to particular device or to a group of devices at a particular priority level. In addition to providing for programmable allocation of bus bandwidth, the arbiter of the present invention permits the number of clock cycles allocated per bus window for one requesting device to be different from the number of clock cycles allocated per bus window for another device. In this manner, the size of the bus window can be designed to accommodate the individual requirements of each device permitting maximization of both the device's and the system's overall efficiency.
摘要翻译：本发明涉及用作仲裁器的可编程逻辑电路，以控制对共享资源的访问，例如，系统总线，由计算机系统中的N个设备。根据本发明的可编程仲裁器实现具有足够灵活性的逻辑设计，以容纳并选择性地并入包括直接优先方案，可编程仲裁和旋转优先权仲裁方案的若干不同仲裁方案的特征。除了这些仲裁方案之外，本发明的仲裁器还支持扩展的可编程仲裁方案，由此即使在请求对共享资源的访问的设备已经占用其分配的带宽份额的情况下，也可以授予对资源的访问权限没有其他请求访问共享资源的设备。此外，可以将总线带宽分配给特定设备或特定优先级的一组设备。除了提供总线带宽的可编程分配之外，本发明的仲裁器允许一个请求设备每总线窗口分配的时钟周期数量与另一个设备每总线窗口分配的时钟周期数不同。以这种方式，总线窗口的尺寸可以被设计为适应每个设备的个体要求，允许设备和系统的整体效率最大化。

4. 发明申请

US20120150527A1 STORAGE PERIPHERAL DEVICE EMULATION 审中-公开
标题翻译：存储外围设备仿真
公开(公告)号：US20120150527A1
公开(公告)日：2012-06-14
申请号：US13390787
申请日：2010-08-20
申请人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
发明人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
IPC分类号： G06F9/455
CPC分类号： G06F3/0632 , G06F3/0607 , G06F3/0683
摘要： An emulation system (1) comprises a programming system (2) made up of a laptop computer (2(a)) and a central server (2(b)), an interrogation station (3), and a programmable storage peripheral device (4). The system (1) links with an existing disk storage peripheral device (10) to retrieve characterisation data, and upload it to the central server (2(b)). The laptop computer (2(a)) then retrieves the characterization data and then programs the programmable device (4) to emulate the full functionality of the pre-existing computer storage peripheral (10). The device (4) is programmed by the host computer (2) to fully replicate characteristics including electrical and timing characteristics and command responses. The programmable device (4) does not have a disk drive, the only storage components being solid state non-volatile memory components, in this embodiment flash memory and volatile components including DRAM. The flash components include mostly NAND flash, but also NOR flash.
摘要翻译：仿真系统（1）包括由膝上型计算机（2（a））和中央服务器（2（b））组成的编程系统（2），询问站（3）和可编程存储外围设备 4）。系统（1）与现有的磁盘存储外围设备（10）链接以检索表征数据，并将其上传到中央服务器（2（b））。膝上型计算机（2（a））然后检索表征数据，然后对可编程设备（4）进行编程，以模拟预先存在的计算机存储外围设备（10）的全部功能。设备（4）由主计算机（2）编程，以完全复制包括电气和定时特性以及命令响应的特性。可编程器件（4）没有磁盘驱动器，唯一的存储组件是固态非易失性存储器组件，在这个实施例中，闪速存储器和包括DRAM的易失性组件。闪存组件主要包括NAND闪存，也包括NOR闪存。

5. 发明授权

US06877145B2 Automatic generation of interconnect logic components 有权
标题翻译：自动生成互连逻辑元件
公开(公告)号：US06877145B2
公开(公告)日：2005-04-05
申请号：US09919806
申请日：2001-08-02
申请人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
发明人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
摘要翻译：自动生成片上系统的互连逻辑的程序工具基于运行核心库和需要核心之间的所有数据交换的架构，通过可能是“片外”的共享存储器进行。该架构包括用于具有连续级别的仲裁来访问存储器的数据聚合技术。

6. 发明授权

US06684258B1 Stackable ring network including burst transmission of data packet 失效
标题翻译：可堆叠环网包括数据包的突发传输
公开(公告)号：US06684258B1
公开(公告)日：2004-01-27
申请号：US09547759
申请日：2000-04-12
申请人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
发明人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
IPC分类号： G06F1516
CPC分类号： H04L12/433
摘要： A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration. The master unit indicates the nature of the subsequent packet by setting a sequence number in the header of the packet to distinguish it and following packets in a burst from the ‘first’ packet which is the one used to pick up requests from the units that may need to become the master unit.
摘要翻译：可以与其他单元形成环的可堆叠网络单元具有主模式，其中它可以在环上放置分组，使得它们可以最终从其他单元转发，并且可以在其中进行转移请求的重复模式在该仲裁包的头部插入位。如果主单元已经完成了分组的传输，并且优选地，在所需的分组间间隔已经过去之后，它还没有接收到仲裁报头以允许作出可以发送后续分组的仲裁决定。该分组的报头信息向其他单元指示该后续分组是分组的突发的一部分，并且其他单元不应该在该分组的报头中设置请求，因为该分组不会用于仲裁。主单元通过在分组报头中设置序列号来指示后续分组的性质，以便从“第一”分组中突发出来的分组中跟随分组，该分组是用于从可能的单元接收请求的分组需要成为主机。

7. 发明授权

US06587389B2 DRAM refresh command operation 失效
标题翻译： DRAM刷新命令操作
公开(公告)号：US06587389B2
公开(公告)日：2003-07-01
申请号：US09984626
申请日：2001-10-30
申请人： Denise De Paor , Tadhg Creedon
发明人： Denise De Paor , Tadhg Creedon
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018 , G11C7/1072
摘要： A method and apparatus for refresh command operations on an SDRAM that avoids use of refresh commands requiring all banks of the SDRAM to be idle. Burst operation establishes command sequences that include Nop command intervals. Some of these Nop intervals are used to perform operations on a bank other than the one under access for the burst that provide a refresh. ACTIVE followed by PRECHARGE commands are inserted into the command intervals addressed to a refresh address. The refresh addresses are generated externally of the SDRAM and provided to a multiplexer that sequences them with the data addresses. A secondary timer checks that required refresh has occurred and prioritizes the refresh addresses over data addresses in the multiplexer in the event that a refresh has not been completed shortly before a maximum refresh interval.
摘要翻译：一种用于SDRAM上的刷新命令操作的方法和装置，其避免使用需要SDRAM的所有存储单元的刷新命令。空行操作建立包括Nop命令间隔的命令序列。这些Nop间隔中的一些用于对提供刷新的突发的除访问之外的银行执行操作。 ACTIVE接着PRECHARGE命令被插入到寻址到刷新地址的命令间隔中。刷新地址由SDRAM的外部产生，并提供给将其与数据地址进行排序的多路复用器。如果在最大刷新间隔之前不完成刷新的情况下，辅助计时器将检查是否发生了所需的刷新，并将刷新地址优先于多路复用器中的数据地址。

8. 发明授权

US5987507A Multi-port communication network device including common buffer memory with threshold control of port packet counters 有权
标题翻译：多端口通信网络设备包括具有端口分组计数器阈值控制的公共缓冲存储器
公开(公告)号：US5987507A
公开(公告)日：1999-11-16
申请号：US222359
申请日：1998-12-29
申请人： Tadhg Creedon , Paul J. Moran , Graeme J. McKerrel
发明人： Tadhg Creedon , Paul J. Moran , Graeme J. McKerrel
IPC分类号： G06F5/06 , H04L12/70 , H04L12/801 , H04L12/835 , H04L12/861 , H04L12/863 , H04L12/879 , H04Q11/04 , G06F13/00
CPC分类号： H04L49/901 , G06F5/065 , H04L47/10 , H04L47/30 , H04L47/6225 , H04L49/90 , H04L49/9047 , H04L49/9078 , H04Q11/0478 , H04L2012/5682
摘要： A network device for use in a data communication network comprises: a multiplicity of ports capable of receiving input data; a common buffer memory for storing in respective buffers data received by the input ports; and processing system for controlling the writing of data into buffers and the reading of data from said buffers. The processing system determines whether the extent of occupation of the common buffer memory exceeds a threshold defined to represent congestion of the memory. Counter system enabled by the processing system on detection of the aforementioned threshold count units of input data through the respective ports, the processing system decrementing these counters as data is read out from the common buffer memory.
摘要翻译：一种用于数据通信网络的网络设备包括：能够接收输入数据的多个端口; 一个公共缓冲存储器，用于存储各个缓冲器中由输入端口接收的数据; 以及用于控制将数据写入缓冲器和从所述缓冲器读取数据的处理系统。处理系统确定公用缓冲存储器的占用范围是否超出了定义为表示存储器拥塞的阈值。由处理系统在通过各个端口检测到上述输入数据的阈值计数单元时使能的计数器系统，从公共缓冲存储器中读出数据的处理系统将这些计数器递减。

9. 发明授权

US06882661B1 System for detection of asynchronous packet rates and maintenance of maximum theoretical packet rate 有权
标题翻译：用于检测异步包速率和维持最大理论包速率的系统
公开(公告)号：US06882661B1
公开(公告)日：2005-04-19
申请号：US09662157
申请日：2000-09-14
申请人： Tadhg Creedon , Denise De Paor , Fergus Casey
发明人： Tadhg Creedon , Denise De Paor , Fergus Casey
IPC分类号： H04L7/02 , H04L7/04 , H04Q11/04 , H04J3/07
CPC分类号： H04Q11/0421 , H04L7/02 , H04L2007/045 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13214 , H04Q2213/13216 , H04Q2213/1332 , H04Q2213/13322 , H04Q2213/1336
摘要： A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.
摘要翻译：系统将包括由非分组字分离的数据分组的数据流从第一时钟域传送到第二时钟域。它包括弹性缓冲器，数据流在第一时钟域中的时钟频率的控制下以循环序列写入到该弹性缓冲器中，并且在时钟频率的控制下以循环序列读出数据流第二个域名监视两个序列以提供指示读取序列接近写入序列的预期信号。非分组字被插入到第一域中的数据流中。在第二时钟域中，检测插入的非分组字的存在，并使缓冲器推进读取周期，从而丢弃所插入的非分组字。

10. 发明授权

US06552590B2 Clocking scheme for ASIC 失效
标题翻译： ASIC时钟方案
公开(公告)号：US06552590B2
公开(公告)日：2003-04-22
申请号：US09879065
申请日：2001-06-13
申请人： Susan M Pratt , Vincent Gavin , Tadhg Creedon , Suzanne M Hughes , Mike Lardner , Padraic O'Reilly
发明人： Susan M Pratt , Vincent Gavin , Tadhg Creedon , Suzanne M Hughes , Mike Lardner , Padraic O'Reilly
IPC分类号： H03K300
CPC分类号： G06F5/06 , G06F1/12
摘要： A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.
摘要翻译：芯片系统的时钟方案，其中系统时钟的积分子倍数在系统时钟的奇数正边缘上具有正边沿，在偶数正边缘上具有负边沿在不同频率的块之间的数据传输由高频块的状态机，并且可以在没有弹性缓冲器和/或同步器的情况下实现。

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