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1. 发明授权

US5729702A Multi-level round robin arbitration system 失效
标题翻译：多级循环仲裁系统
公开(公告)号：US5729702A
公开(公告)日：1998-03-17
申请号：US772782
申请日：1996-12-24
申请人： Tadhg Creedon , Richard A. Gahan , Fearghal Morgan
发明人： Tadhg Creedon , Richard A. Gahan , Fearghal Morgan
IPC分类号： G06F13/364 , G06F13/14 , G06F13/37
CPC分类号： G06F13/364
摘要： Arbitration means for arbitrating between computer devices A to F which compete for access to a common bus. The system provides cascaded round-robin units. Unit RR1 has ports A, B, C, and X in sequence, with port X coupled to round-robin unit RR2, which has ports D, E, F in sequence. On each cycling of unit RR1 past C to A, unit RR2 is checked and the next one of devices D to F (in the sequence determined by unit RR2) has the opportunity of bus access. A gating circuit 13 can further restrict bus accessing by unit RR2's devices, by timing or counter control. A third round-robin unit can be added coupled to unit RR1 (which would have ports A, B, C, X,Y) or to unit RR2 (which would have ports D, E, F, Y). The assignment of devices to ports can be controllable by a matrix switch and device assignment memory.
摘要翻译：仲裁意味着在计算机设备A到F之间进行仲裁，竞争访问公共总线。该系统提供级联循环单元。单元RR1依次具有端口A，B，C和X，端口X与循环单元RR2相连，其具有端口D，E，F。在单元RR1经过C到A的每个循环之后，检查单元RR2，并且设备D到F中的下一个（由单元RR2确定的顺序）具有总线访问的机会。选通电路13可以通过定时或反向控制来进一步限制通过单元RR2的设备的总线访问。可以将第三循环单元添加到单元RR1（其将具有端口A，B，C，X，Y）或单元RR2（其将具有端口D，E，F，Y）。设备到端口的分配可以通过矩阵开关和设备分配存储器来控制。

2. 发明授权

US5568476A Method and apparatus for avoiding packet loss on a CSMA/CD-type local area network using receive-sense-based jam signal 失效
标题翻译：使用基于接收传感的阻塞信号在CSMA / CD型局域网上避免分组丢失的方法和装置
公开(公告)号：US5568476A
公开(公告)日：1996-10-22
申请号：US329714
申请日：1994-10-26
申请人： William P. Sherer , Richard A. Gahan , John F. Hickey
发明人： William P. Sherer , Richard A. Gahan , John F. Hickey
IPC分类号： H04L12/413 , H04L12/46 , H04L12/56 , H04Q11/04
CPC分类号： H04L47/10 , H04L12/413 , H04L47/135 , H04L47/2416 , H04L49/351 , H04L12/40013 , H04L12/46 , H04L49/205 , H04L49/552
摘要： An Ethernet network or other CSMA/CD network includes a hub that is modified to generate a jamming signal on a communication line when a packet received over that line is directed to an unavailable destination. The destination may be unavailable due to full transmit buffers, full receive buffers, or congestion in other parts of the hub architecture. Jamming is detected by the source node as a collision and causes retransmission of the packet from the source node. The decision to jam may include a determination of the packet's priority which may be determined based on the packet's destination or source address.
摘要翻译：以太网或其他CSMA / CD网络包括一个集线器，当通过该线路接收的分组指向不可用的目的地时，该集线器被修改以在通信线路上产生干扰信号。由于完整的传输缓冲区，完整的接收缓冲区或集线器架构的其他部分的拥塞，目的地可能不可用。源节点检测到干扰作为冲突，并导致来自源节点的分组的重传。阻塞的决定可以包括可以基于分组的目的地或源地址来确定分组的优先级的确定。

3. 发明授权

US07420968B2 High-speed switch architecture 有权
标题翻译：高速交换架构
公开(公告)号：US07420968B2
公开(公告)日：2008-09-02
申请号：US10456702
申请日：2003-06-06
申请人： Bryan J. Donoghue , Richard A. Gahan , Kam Choi , Edele O'Malley , Eugene O'Neill
发明人： Bryan J. Donoghue , Richard A. Gahan , Kam Choi , Edele O'Malley , Eugene O'Neill
IPC分类号： H04L12/50 , H04Q11/00
CPC分类号： H04L49/1515
摘要： A system of switch modules contains input demultiplexers connected to ports on each of the modules and output multiplexers connected to each of the modules. Each module has output and input interfaces for mesh links and at least one output interface is looped back to an input interface on the same module. The arrangement reduces module-to-module traffic and corresponding increases the transmit bandwidth of a module.
摘要翻译：开关模块的系统包括连接到每个模块上的端口的输入解复用器和连接到每个模块的输出多路复用器。每个模块都具有用于网格链接的输出和输入接口，并且至少一个输出接口循环回相同模块上的输入接口。该装置减少了模块到模块的流量，并且相应地增加了模块的传输带宽。

4. 发明授权

US06915448B2 Storage disk failover and replacement system 有权
标题翻译：存储磁盘故障切换和更换系统
公开(公告)号：US06915448B2
公开(公告)日：2005-07-05
申请号：US10128352
申请日：2002-04-24
申请人： Ciaran Murphy , Richard A Gahan , John Healy
发明人： Ciaran Murphy , Richard A Gahan , John Healy
IPC分类号： G06F11/00 , G06F11/20 , H04L1/22
CPC分类号： G06F11/1662 , G06F11/2094
摘要： A storage assembly includes a plurality of multi-unit storage device is provided with a failover procedure that does not require hot-swap capability. Individual units are aggregated into a storage array by an aggregation procedure such as RAID. When a failure occurs data from the failed unit is transferred to a hot spare unit. Also, data from other units is transferred by simulating failure of those units and then the complete device can be removed. In small storage networks all the units may be aggregated as a single array and a spare auxiliary device is summoned and integrated into the array prior to the simulated failure. In larger systems there may be two layers of aggregation and failover is run by the second level of aggregation.
摘要翻译：存储组件包括多个多单元存储设备，其具有不需要热插拔能力的故障转移过程。通过诸如RAID的聚合过程将单个单元聚合到存储阵列中。发生故障时，故障单元的数据传输到热备用单元。此外，通过模拟这些单元的故障来传输来自其他单元的数据，然后可以去除完整的设备。在小型存储网络中，所有单元可以被聚合为单个阵列，并且备用辅助设备在模拟故障之前被召唤并集成到阵列中。在较大的系统中，可能有两层聚合，故障转移由第二级聚合运行。

5. 发明授权

US06504843B1 System and method for dynamically mapping a high speed link to a multiplicity of low speed trunked links 失效
标题翻译：将高速链路动态映射到多个低速中继链路的系统和方法
公开(公告)号：US06504843B1
公开(公告)日：2003-01-07
申请号：US09353606
申请日：1999-07-14
申请人： Con Cremin , Sorcha O'Callaghan , David Nolan , Raymond Beechinor , Richard A Gahan
发明人： Con Cremin , Sorcha O'Callaghan , David Nolan , Raymond Beechinor , Richard A Gahan
IPC分类号： H04L1228
CPC分类号： H04L47/621 , H04L45/745 , H04L47/50 , H04L47/521 , H04L47/6225 , H04L49/30 , H04L49/351 , H04L49/901
摘要： A method for distributing addressed data packets from an input channel to a multiplicity of packet queues includes receiving said addressed data packets and, responsive to first hashed addresses, distributing the addressed data packets to said queues in accordance with said first hashed addresses. A first hash function is applied to selected address data of each of said addressed data packets to produce said first hashed addresses. At the same time a succession of different hash functions is applied to said selected address data in each of the packets to produce second hashed addresses and occurrences of each of the second hashed addresses are counted so as to obtain for each of said different hash functions a respective one of a plurality of set of counts, each such set representing the distribution of said packets that would occur in said queues if the respective one of the different hash functions had been applied to said addressed data packets. The sets of counts are analyzed to determined which one of them represents a best distribution of said packets and the hash function associated with the best distribution is applied to incoming packets in place of the said first hash function.
摘要翻译：一种用于将寻址的数据分组从输入信道分配到多个分组队列的方法包括接收所述寻址的数据分组，并且响应于第一哈希地址，根据所述第一散列地址将寻址的数据分组分配到所述队列。第一散列函数被应用于每个所述寻址的数据分组的选择的地址数据以产生所述第一散列地址。同时，对每个分组中的所述选择的地址数据应用一系列不同的散列函数以产生第二散列地址，并对每个第二散列地址的出现进行计数，以便为每个所述不同的散列函数a 相应的多个计数集合中的一个，每个这样的集合表示如果不同散列函数中的相应一个已被应用于所述寻址的数据分组，则将在所述队列中发生的所述分组的分布。分析计数集合以确定其中哪一个表示所述分组的最佳分布，并且将与最佳分布相关联的散列函数应用于输入分组而不是所述第一哈希函数。

6. 发明授权

US07065670B2 Server monitoring and failover mechanism 有权
标题翻译：服务器监控和故障转移机制
公开(公告)号：US07065670B2
公开(公告)日：2006-06-20
申请号：US10284475
申请日：2002-10-31
申请人： Richard A. Gahan , John Hickey
发明人： Richard A. Gahan , John Hickey
IPC分类号： G06F11/00
CPC分类号： G06F11/2023 , G06F11/2028 , G06F11/2035 , H04L67/1002
摘要： Access of a malfunctioning server to a data storage facility is blocked. Characteristics such as IAmAlive signals from a server are monitored and when out of profile a malfunction is indicated and data access of that server is inhibited. Characteristics continue to be monitored for a return from the malfunction. The system can be used in a resilient cluster of servers to shut out a malfunctioning server and enable its recovery to be indicated so as to enable readmittance to the cluster.
摘要翻译：对数据存储设备的故障服务器的访问被阻止。监视来自服务器的诸如IAmAlive信号的特征，并且当外部配置文件出现故障并且禁止该服务器的数据访问时。特性继续受到监控，从故障返回。该系统可用于一个有弹性的服务器集群，以关闭故障服务器，并使其恢复被指示，以便启用对集群的导纳。

7. 发明授权

US06779056B2 Direct data placement and message reassembly 失效
标题翻译：直接数据放置和消息重新组装
公开(公告)号：US06779056B2
公开(公告)日：2004-08-17
申请号：US09897044
申请日：2001-07-03
申请人： Eugene O'Neill , Richard A Gahan
发明人： Eugene O'Neill , Richard A Gahan
IPC分类号： G06F300
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9063 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/163
摘要： A direct data placement implementation for a data reassembly process. Data within a protocol data unit is placed directly in preassigned application buffers. The network interface card has buffer space into which message headers, segment headers and indicators of escaped data and size of escaped data are placed. A single buffer can contain this information for a complete PDU (or message) and is handed over to enable the next process to run on a per message basis.
摘要翻译：数据重组过程的直接数据放置实现。协议数据单元中的数据直接放置在预先分配的应用程序缓冲区中。网络接口卡具有缓冲空间，消息头，段头和转义数据的指示符以及转义数据的大小被放置到其中。单个缓冲区可以包含用于完整PDU（或消息）的该信息，并且被移交以使下一个进程能够在每个消息的基础上运行。

8. 发明授权

US5148112A Efficient arbiter 失效
标题翻译：有效的仲裁者
公开(公告)号：US5148112A
公开(公告)日：1992-09-15
申请号：US723055
申请日：1991-06-28
申请人： Richard A. Gahan
发明人： Richard A. Gahan
IPC分类号： G06F9/48 , G06F9/46 , G06F13/362 , G06F13/364 , H03K5/22
CPC分类号： G06F13/364 , H03K5/22
摘要： A logic circuit for use as an arbiter to arbitrate among N devices of a computer system for access to a shared resource. The arbiter generates state variables to represent arbitration win information. The state variables are generated through the use of request for arbitration signals input to the arbiter, present values of the state variables and internally generated intermediate arbitration win signals to provide a cost effective, efficient implementation of the logic required for the arbitration in a smaller physical solution for the arbitration logic.

9. 发明授权

US06804804B2 Calculation and transmission of error check codes 失效
标题翻译：错误检查代码的计算和传输
公开(公告)号：US06804804B2
公开(公告)日：2004-10-12
申请号：US09909756
申请日：2001-07-23
申请人： Richard A Gahan , Eugene O'Neill
发明人： Richard A Gahan , Eugene O'Neill
IPC分类号： G08C2502
CPC分类号： H04L69/16 , H04L1/1874 , H04L69/169
摘要： A method of transmitting data (1) generated in an upper layer protocol such as iSCSI in a transport protocol such as TCP or SCTP, without requiring separate reads for check code generation and transmission. The upper layer protocol data is read into a transmission engine (5) that calculates the error check codes and inserts them into the transport protocol transmission. To prevent having to recalculate error codes in the event of loss of transmitted data and a retransmission request, the engine preferably also writes the error check codes into the memory so that the can be retrieved if retransmission is necessary.
摘要翻译：在诸如TCP或SCTP的传输协议中发送在诸如iSCSI的上层协议（诸如iSCSI）中生成的数据（1）的方法，而不需要用于校验码生成和传输的单独读取。将上层协议数据读入传输引擎（5），该传输引擎计算错误校验码并将其插入到传输协议传输中。为了防止在丢失发送数据和重发请求的情况下重新计算错误代码，引擎优选还将错误校验码写入存储器，以便如果需要重传则可以检索该错误代码。

10. 发明授权

US6125466A DRAM parity protection scheme 失效
标题翻译： DRAM奇偶校验保护方案
公开(公告)号：US6125466A
公开(公告)日：2000-09-26
申请号：US346311
申请日：1994-11-28
申请人： Ciaran B. Close , Richard A. Gahan , Bryan T. Campbell
发明人： Ciaran B. Close , Richard A. Gahan , Bryan T. Campbell
IPC分类号： G06F11/10 , H03M13/11 , H03M13/29 , H03M13/00
CPC分类号： H03M13/2909 , G06F11/1008
摘要： A scheme for protecting memory stored in a DRAM using a combination of horizontal and vertical parity data to detect and correct errors in a protected space of memory in which code is stored. The DRAM memory of this scheme is architected with the code stored in horizontally contiguous bytes and the vertical parity, generated when the code is compiled, also stored in horizontally contiguous bytes, but in a row of DRAM memory separate from those in which the code is stored.
摘要翻译：一种用于使用水平和垂直奇偶校验数据的组合保护存储在DRAM中的存储器的方案，以检测和校正存储代码的存储器的受保护空间中的错误。该方案的DRAM存储器被构造为存储在水平连续的字节中的代码，并且当代码被编译时产生的垂直奇偶校验也存储在水平连续的字节中，但是存储在一行DRAM存储器中，其中代码是存储。

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