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1. 发明申请

US20120150527A1 STORAGE PERIPHERAL DEVICE EMULATION 审中-公开
标题翻译：存储外围设备仿真
公开(公告)号：US20120150527A1
公开(公告)日：2012-06-14
申请号：US13390787
申请日：2010-08-20
申请人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
发明人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
IPC分类号： G06F9/455
CPC分类号： G06F3/0632 , G06F3/0607 , G06F3/0683
摘要： An emulation system (1) comprises a programming system (2) made up of a laptop computer (2(a)) and a central server (2(b)), an interrogation station (3), and a programmable storage peripheral device (4). The system (1) links with an existing disk storage peripheral device (10) to retrieve characterisation data, and upload it to the central server (2(b)). The laptop computer (2(a)) then retrieves the characterization data and then programs the programmable device (4) to emulate the full functionality of the pre-existing computer storage peripheral (10). The device (4) is programmed by the host computer (2) to fully replicate characteristics including electrical and timing characteristics and command responses. The programmable device (4) does not have a disk drive, the only storage components being solid state non-volatile memory components, in this embodiment flash memory and volatile components including DRAM. The flash components include mostly NAND flash, but also NOR flash.
摘要翻译：仿真系统（1）包括由膝上型计算机（2（a））和中央服务器（2（b））组成的编程系统（2），询问站（3）和可编程存储外围设备 4）。系统（1）与现有的磁盘存储外围设备（10）链接以检索表征数据，并将其上传到中央服务器（2（b））。膝上型计算机（2（a））然后检索表征数据，然后对可编程设备（4）进行编程，以模拟预先存在的计算机存储外围设备（10）的全部功能。设备（4）由主计算机（2）编程，以完全复制包括电气和定时特性以及命令响应的特性。可编程器件（4）没有磁盘驱动器，唯一的存储组件是固态非易失性存储器组件，在这个实施例中，闪速存储器和包括DRAM的易失性组件。闪存组件主要包括NAND闪存，也包括NOR闪存。

2. 发明授权

US06877145B2 Automatic generation of interconnect logic components 有权
标题翻译：自动生成互连逻辑元件
公开(公告)号：US06877145B2
公开(公告)日：2005-04-05
申请号：US09919806
申请日：2001-08-02
申请人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
发明人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
摘要翻译：自动生成片上系统的互连逻辑的程序工具基于运行核心库和需要核心之间的所有数据交换的架构，通过可能是“片外”的共享存储器进行。该架构包括用于具有连续级别的仲裁来访问存储器的数据聚合技术。

3. 发明授权

US06684258B1 Stackable ring network including burst transmission of data packet 失效
标题翻译：可堆叠环网包括数据包的突发传输
公开(公告)号：US06684258B1
公开(公告)日：2004-01-27
申请号：US09547759
申请日：2000-04-12
申请人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
发明人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
IPC分类号： G06F1516
CPC分类号： H04L12/433
摘要： A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration. The master unit indicates the nature of the subsequent packet by setting a sequence number in the header of the packet to distinguish it and following packets in a burst from the ‘first’ packet which is the one used to pick up requests from the units that may need to become the master unit.
摘要翻译：可以与其他单元形成环的可堆叠网络单元具有主模式，其中它可以在环上放置分组，使得它们可以最终从其他单元转发，并且可以在其中进行转移请求的重复模式在该仲裁包的头部插入位。如果主单元已经完成了分组的传输，并且优选地，在所需的分组间间隔已经过去之后，它还没有接收到仲裁报头以允许作出可以发送后续分组的仲裁决定。该分组的报头信息向其他单元指示该后续分组是分组的突发的一部分，并且其他单元不应该在该分组的报头中设置请求，因为该分组不会用于仲裁。主单元通过在分组报头中设置序列号来指示后续分组的性质，以便从“第一”分组中突发出来的分组中跟随分组，该分组是用于从可能的单元接收请求的分组需要成为主机。

4. 发明授权

US06587389B2 DRAM refresh command operation 失效
标题翻译： DRAM刷新命令操作
公开(公告)号：US06587389B2
公开(公告)日：2003-07-01
申请号：US09984626
申请日：2001-10-30
申请人： Denise De Paor , Tadhg Creedon
发明人： Denise De Paor , Tadhg Creedon
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018 , G11C7/1072
摘要： A method and apparatus for refresh command operations on an SDRAM that avoids use of refresh commands requiring all banks of the SDRAM to be idle. Burst operation establishes command sequences that include Nop command intervals. Some of these Nop intervals are used to perform operations on a bank other than the one under access for the burst that provide a refresh. ACTIVE followed by PRECHARGE commands are inserted into the command intervals addressed to a refresh address. The refresh addresses are generated externally of the SDRAM and provided to a multiplexer that sequences them with the data addresses. A secondary timer checks that required refresh has occurred and prioritizes the refresh addresses over data addresses in the multiplexer in the event that a refresh has not been completed shortly before a maximum refresh interval.
摘要翻译：一种用于SDRAM上的刷新命令操作的方法和装置，其避免使用需要SDRAM的所有存储单元的刷新命令。空行操作建立包括Nop命令间隔的命令序列。这些Nop间隔中的一些用于对提供刷新的突发的除访问之外的银行执行操作。 ACTIVE接着PRECHARGE命令被插入到寻址到刷新地址的命令间隔中。刷新地址由SDRAM的外部产生，并提供给将其与数据地址进行排序的多路复用器。如果在最大刷新间隔之前不完成刷新的情况下，辅助计时器将检查是否发生了所需的刷新，并将刷新地址优先于多路复用器中的数据地址。

5. 发明授权

US5987507A Multi-port communication network device including common buffer memory with threshold control of port packet counters 有权
标题翻译：多端口通信网络设备包括具有端口分组计数器阈值控制的公共缓冲存储器
公开(公告)号：US5987507A
公开(公告)日：1999-11-16
申请号：US222359
申请日：1998-12-29
申请人： Tadhg Creedon , Paul J. Moran , Graeme J. McKerrel
发明人： Tadhg Creedon , Paul J. Moran , Graeme J. McKerrel
IPC分类号： G06F5/06 , H04L12/70 , H04L12/801 , H04L12/835 , H04L12/861 , H04L12/863 , H04L12/879 , H04Q11/04 , G06F13/00
CPC分类号： H04L49/901 , G06F5/065 , H04L47/10 , H04L47/30 , H04L47/6225 , H04L49/90 , H04L49/9047 , H04L49/9078 , H04Q11/0478 , H04L2012/5682
摘要： A network device for use in a data communication network comprises: a multiplicity of ports capable of receiving input data; a common buffer memory for storing in respective buffers data received by the input ports; and processing system for controlling the writing of data into buffers and the reading of data from said buffers. The processing system determines whether the extent of occupation of the common buffer memory exceeds a threshold defined to represent congestion of the memory. Counter system enabled by the processing system on detection of the aforementioned threshold count units of input data through the respective ports, the processing system decrementing these counters as data is read out from the common buffer memory.
摘要翻译：一种用于数据通信网络的网络设备包括：能够接收输入数据的多个端口; 一个公共缓冲存储器，用于存储各个缓冲器中由输入端口接收的数据; 以及用于控制将数据写入缓冲器和从所述缓冲器读取数据的处理系统。处理系统确定公用缓冲存储器的占用范围是否超出了定义为表示存储器拥塞的阈值。由处理系统在通过各个端口检测到上述输入数据的阈值计数单元时使能的计数器系统，从公共缓冲存储器中读出数据的处理系统将这些计数器递减。

6. 发明授权

US07656330B2 Automatic range shift system and method for an analog to digital converter 有权
标题翻译：用于模数转换器的自动量程移位系统和方法
公开(公告)号：US07656330B2
公开(公告)日：2010-02-02
申请号：US12154330
申请日：2008-05-22
申请人： John O'Dowd , Kevin Jennings , Tadhg Creedon
发明人： John O'Dowd , Kevin Jennings , Tadhg Creedon
IPC分类号： H03M3/00
CPC分类号： H03M1/181
摘要： Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.
摘要翻译：模数转换器（ADC）的自动量程移位包括组合外部模拟输入和DAC输出以向ADC提供输入，检测ADC的输出范围是否高于预定的上限范围或低于并且如果ADC输出高于上限范围限制，则产生调整代码以增加DAC输出，并且如果ADC输出低于ADC输出的下限范围以减小DAC输出，则在ADC输出高于上限，并且当ADC输出低于下限以增加ADC输入，以将ADC输入保持在ADC范围内。

7. 发明申请

US20080291067A1 Automatic range shift system and method for an Analog to Digital Converter 有权
标题翻译：自动量程移位系统和模数转换器的方法
公开(公告)号：US20080291067A1
公开(公告)日：2008-11-27
申请号：US12154330
申请日：2008-05-22
申请人： John O'Dowd , Kevin Jennings , Tadhg Creedon
发明人： John O'Dowd , Kevin Jennings , Tadhg Creedon
IPC分类号： H03M1/06 , H03M1/34
CPC分类号： H03M1/181
摘要： Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.
摘要翻译：模数转换器（ADC）的自动量程移位包括组合外部模拟输入和DAC输出以向ADC提供输入，检测ADC的输出范围是否高于预定的上限范围或低于并且如果ADC输出高于上限范围限制，则产生调整代码以增加DAC输出，并且如果ADC输出低于ADC输出的下限范围以减小DAC输出，则在ADC输出高于上限，并且当ADC输出低于下限以增加ADC输入，以将ADC输入保持在ADC范围内。

8. 发明授权

US06718411B2 Asic system architecture including data aggregation technique 失效
标题翻译： Asic系统架构包括数据聚合技术
公开(公告)号：US06718411B2
公开(公告)日：2004-04-06
申请号：US09893659
申请日：2001-06-29
申请人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
发明人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
IPC分类号： G06F1336
CPC分类号： G06F17/5045
摘要： An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.
摘要翻译：一种用于芯片上系统的架构，其中功能核心具有用于与公共总线系统兼容的封装器，并且总线系统包括用于不同速度和/或总线宽度的总线事务的聚合器。

9. 发明授权

US6101554A Apparatus for controlling data flow using lookup tables to link incoming packets directly to output ports 失效
标题翻译：用于使用查找表来控制数据流的装置，以将输入的分组直接链接到输出端口
公开(公告)号：US6101554A
公开(公告)日：2000-08-08
申请号：US973177
申请日：1998-06-15
申请人： Tadhg Creedon , Anne O'Connell , Eugene O'Neill , Vincent Gavin , John Hickey , Richard Gahan , William P Sherer
发明人： Tadhg Creedon , Anne O'Connell , Eugene O'Neill , Vincent Gavin , John Hickey , Richard Gahan , William P Sherer
IPC分类号： G06F13/362 , G06F13/40 , G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： Apparatus for monitoring and controlling data flow ina computer network device having a plurality of parts comprises control means for directly linking ports together on the basis of additional information stored in the control means whereby incoming packets are linked directly to an utput port to achieve high performance. The additional information is stored in one more look-up tables additional to the normal CAm with the or each table addressed by separate processing. This allows the implementation to be in hardware rather than in software.
摘要翻译： PCT No.PCT / EP96 / 02338 Sec。 371日期1998年6月15日第 102（e）1998年6月15日PCT PCT 1996年5月30日提交PCT公布。公开号WO96 / 38792 日期1996年12月5日用于在具有多个部分的计算机网络设备中监视和控制数据流的装置包括控制装置，用于基于存储在控制装置中的附加信息直接将端口连接在一起，由此输入分组直接连接到输出端口实现高性能。附加信息存储在除正常CAm之外的另外一个查找表中，其中每个表通过单独处理寻址。这允许实现在硬件而不是软件。

10. 发明授权

US5453983A Port controller 失效
标题翻译：端口控制器
公开(公告)号：US5453983A
公开(公告)日：1995-09-26
申请号：US130609
申请日：1993-10-01
申请人： Anne O'Connell , John Hickey , Tadhg Creedon
发明人： Anne O'Connell , John Hickey , Tadhg Creedon
IPC分类号： G06F13/362 , G06F13/18 , G06F13/376 , H04J3/17
CPC分类号： G06F13/362
摘要： Two devices HR and FR are coupled to a bus with a common memory via a port controller. Device HR requires a high (or maximum) average rate of access, device FR requires a fast response (minimum latency) in establishing access. Request signals HRQ, FRQ from the devices are latched by latches 20 and 21, passed as HRX, FRX through an arbitration or resolver circuit 22 as HRY, FRY to a sequence control unit 23 to initiate an access cycle. Cycle timing is determined by a delay line timebase circuit 24, which responds to a single change of level of a signal DLY (in either direction). Latch 21, when set, generates an request pending signal FRRP which is fed to the HR device to cause it to increase its cycle length so that the FR access cycle will finish before the next HR access cycle is initiated.
摘要翻译：两个设备HR和FR通过端口控制器耦合到具有公共存储器的总线。设备HR需要高（或最大）平均访问速率，设备FR需要在建立访问时的快速响应（最小延迟）。来自装置的请求信号HRQ，FRQ由锁存器20和21锁存，通过作为HRY，FRY的仲裁或解析器电路22作为HRX，FRX传递到序列控制单元23以启动访问周期。周期定时由延迟线时基电路24确定，延迟线时基电路24响应于信号DLY（在任一方向上）的电平的单次改变。锁存器21当被设置时产生请求等待信号FRRP，其被馈送到HR设备以使其增加其周期长度，使得FR访问周期将在下一个HR访问周期启动之前完成。

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