专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06718411B2 Asic system architecture including data aggregation technique 失效
标题翻译： Asic系统架构包括数据聚合技术
公开(公告)号：US06718411B2
公开(公告)日：2004-04-06
申请号：US09893659
申请日：2001-06-29
申请人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
发明人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
IPC分类号： G06F1336
CPC分类号： G06F17/5045
摘要： An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.
摘要翻译：一种用于芯片上系统的架构，其中功能核心具有用于与公共总线系统兼容的封装器，并且总线系统包括用于不同速度和/或总线宽度的总线事务的聚合器。

2. 发明授权

US06882661B1 System for detection of asynchronous packet rates and maintenance of maximum theoretical packet rate 有权
标题翻译：用于检测异步包速率和维持最大理论包速率的系统
公开(公告)号：US06882661B1
公开(公告)日：2005-04-19
申请号：US09662157
申请日：2000-09-14
申请人： Tadhg Creedon , Denise De Paor , Fergus Casey
发明人： Tadhg Creedon , Denise De Paor , Fergus Casey
IPC分类号： H04L7/02 , H04L7/04 , H04Q11/04 , H04J3/07
CPC分类号： H04Q11/0421 , H04L7/02 , H04L2007/045 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13214 , H04Q2213/13216 , H04Q2213/1332 , H04Q2213/13322 , H04Q2213/1336
摘要： A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.
摘要翻译：系统将包括由非分组字分离的数据分组的数据流从第一时钟域传送到第二时钟域。它包括弹性缓冲器，数据流在第一时钟域中的时钟频率的控制下以循环序列写入到该弹性缓冲器中，并且在时钟频率的控制下以循环序列读出数据流第二个域名监视两个序列以提供指示读取序列接近写入序列的预期信号。非分组字被插入到第一域中的数据流中。在第二时钟域中，检测插入的非分组字的存在，并使缓冲器推进读取周期，从而丢弃所插入的非分组字。

3. 发明授权

US06877145B2 Automatic generation of interconnect logic components 有权
标题翻译：自动生成互连逻辑元件
公开(公告)号：US06877145B2
公开(公告)日：2005-04-05
申请号：US09919806
申请日：2001-08-02
申请人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
发明人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
摘要翻译：自动生成片上系统的互连逻辑的程序工具基于运行核心库和需要核心之间的所有数据交换的架构，通过可能是“片外”的共享存储器进行。该架构包括用于具有连续级别的仲裁来访问存储器的数据聚合技术。

4. 发明授权

US06684258B1 Stackable ring network including burst transmission of data packet 失效
标题翻译：可堆叠环网包括数据包的突发传输
公开(公告)号：US06684258B1
公开(公告)日：2004-01-27
申请号：US09547759
申请日：2000-04-12
申请人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
发明人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
IPC分类号： G06F1516
CPC分类号： H04L12/433
摘要： A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration. The master unit indicates the nature of the subsequent packet by setting a sequence number in the header of the packet to distinguish it and following packets in a burst from the ‘first’ packet which is the one used to pick up requests from the units that may need to become the master unit.
摘要翻译：可以与其他单元形成环的可堆叠网络单元具有主模式，其中它可以在环上放置分组，使得它们可以最终从其他单元转发，并且可以在其中进行转移请求的重复模式在该仲裁包的头部插入位。如果主单元已经完成了分组的传输，并且优选地，在所需的分组间间隔已经过去之后，它还没有接收到仲裁报头以允许作出可以发送后续分组的仲裁决定。该分组的报头信息向其他单元指示该后续分组是分组的突发的一部分，并且其他单元不应该在该分组的报头中设置请求，因为该分组不会用于仲裁。主单元通过在分组报头中设置序列号来指示后续分组的性质，以便从“第一”分组中突发出来的分组中跟随分组，该分组是用于从可能的单元接收请求的分组需要成为主机。

5. 发明授权

US06587389B2 DRAM refresh command operation 失效
标题翻译： DRAM刷新命令操作
公开(公告)号：US06587389B2
公开(公告)日：2003-07-01
申请号：US09984626
申请日：2001-10-30
申请人： Denise De Paor , Tadhg Creedon
发明人： Denise De Paor , Tadhg Creedon
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018 , G11C7/1072
摘要： A method and apparatus for refresh command operations on an SDRAM that avoids use of refresh commands requiring all banks of the SDRAM to be idle. Burst operation establishes command sequences that include Nop command intervals. Some of these Nop intervals are used to perform operations on a bank other than the one under access for the burst that provide a refresh. ACTIVE followed by PRECHARGE commands are inserted into the command intervals addressed to a refresh address. The refresh addresses are generated externally of the SDRAM and provided to a multiplexer that sequences them with the data addresses. A secondary timer checks that required refresh has occurred and prioritizes the refresh addresses over data addresses in the multiplexer in the event that a refresh has not been completed shortly before a maximum refresh interval.
摘要翻译：一种用于SDRAM上的刷新命令操作的方法和装置，其避免使用需要SDRAM的所有存储单元的刷新命令。空行操作建立包括Nop命令间隔的命令序列。这些Nop间隔中的一些用于对提供刷新的突发的除访问之外的银行执行操作。 ACTIVE接着PRECHARGE命令被插入到寻址到刷新地址的命令间隔中。刷新地址由SDRAM的外部产生，并提供给将其与数据地址进行排序的多路复用器。如果在最大刷新间隔之前不完成刷新的情况下，辅助计时器将检查是否发生了所需的刷新，并将刷新地址优先于多路复用器中的数据地址。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式