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1. 发明授权

US06937624B1 System for manintaining inter-packet gaps in cascade transmission system for packet-based data 失效
标题翻译：用于为基于分组的数据级联传输系统中的分组间间隔的制约
公开(公告)号：US06937624B1
公开(公告)日：2005-08-30
申请号：US09633855
申请日：2000-08-07
申请人： Vincent Gavin
发明人： Vincent Gavin
IPC分类号： H04J3/06 , H04L25/20 , H04J3/12
CPC分类号： H04L25/20 , H04J3/0632
摘要： A unit for receiving and re-transmitting data signals comprising multi-byte packets separated by multi-byte inter-packet gaps includes a FIFO store, a first, write, state machine for controlling the writing of packets into the FIFO and a second, read, state machine for controlling read-out of packets from the FIFO. The first state machine is controlled by a recovered clock and the second state machine is controlled by a local system clock. The first state machine is operative in a writing sequence to write into the FIFO the words of each received packet in successive locations and thereafter to cause the writing into the FIFO of a succession of idle bytes representing a selected inter-packet gap; and the second state machine is operative in response to maintain a reading sequence in arrears of the writing sequence by a selected number of said locations. The arrangement maintains the inter-packet gap despite slight differences between the recovered clock and the system clock.
摘要翻译：用于接收和重新发送数据信号的单元，包括由多字节分组间间隔分隔的多字节分组，包括FIFO存储器，第一写入状态机，用于控制将数据包写入FIFO，第二读取用于控制从FIFO读出数据包的状态机。第一状态机由恢复的时钟控制，第二状态机由本地系统时钟控制。第一状态机以写入顺序操作，以在连续位置中将每个接收到的分组的单词写入FIFO，并且此后将使FIFO写入代表所选择的分组间间隔的一系列空闲字节; 并且所述第二状态机响应于通过选定数目的所述位置保持所述写入序列的拖欠的读取序列而被操作。尽管恢复的时钟和系统时钟之间存在轻微的差异，但这种配置保持了分组间间隔。

2. 发明授权

US06486450B1 Method and apparatus for inducing locally elevated temperatures in an application specific integrated circuit 失效
标题翻译：用于在专用集成电路中诱发局部升高的温度的方法和装置
公开(公告)号：US06486450B1
公开(公告)日：2002-11-26
申请号：US09662114
申请日：2000-09-14
申请人： Una Quinlan , Vincent Gavin , Tadhg Creedon
发明人： Una Quinlan , Vincent Gavin , Tadhg Creedon
IPC分类号： H05B102
CPC分类号： G01R31/2877
摘要： An application specific integrated circuit includes a multiplicity of operative circuit blocks. Disposed in at least one of the blocks is a multiplicity of selectively operative heater modules for providing localised heating within the block. The heater modules may comprise cyclic redundancy code generators each coupled to respond to a system clock, and each heater module may include a system clock divider providing a multiplicity of differently divided clock signals and means for selecting a clock signal for use by the module. The invention is useful in design variable testing to produce variation with temperature of the frequency of an intermittent timing error.
摘要翻译：专用集成电路包括多个操作电路块。设置在至少一个块中的是多个选择性操作的加热器模块，用于在块内提供局部加热。加热器模块可以包括循环冗余码发生器，每个循环冗余码发生器各自耦合以响应于系统时钟，并且每个加热器模块可以包括提供多个不同分割时钟信号的系统时钟分频器和用于选择模块使用的时钟信号的装置。本发明在设计变量测试中可用于产生随间歇定时误差频率的温度变化。

3. 发明授权

US07042889B2 Network switch with parallel working of look-up engine and network processor 有权
公开(公告)号：US07042889B2
公开(公告)日：2006-05-09
申请号：US10086890
申请日：2002-03-04
申请人： Kevin Jennings , Kevin J Hyland , Vincent Gavin
发明人： Kevin Jennings , Kevin J Hyland , Vincent Gavin
IPC分类号： H04L12/28
CPC分类号： H04L45/742 , H04L49/3018 , H04L49/351
摘要： A network switch which allows a network processor to process resultant data from a look-up engine while the look-up engine proceeds to deal with a subsequent packet. The look-up engine stores the resultant data in registers from which the resultant data is written back for the packet if the processor does not intervene. If the processor intervenes it acts on the resultant data, which is written back for the packet only after the processor has finished. A system of pointers and busy bits ensures that the packet is not forwarded until the look-up engine and (if required) the network processor have completed their operations in relation to the packet.

4. 发明授权

US06552590B2 Clocking scheme for ASIC 失效
标题翻译： ASIC时钟方案
公开(公告)号：US06552590B2
公开(公告)日：2003-04-22
申请号：US09879065
申请日：2001-06-13
申请人： Susan M Pratt , Vincent Gavin , Tadhg Creedon , Suzanne M Hughes , Mike Lardner , Padraic O'Reilly
发明人： Susan M Pratt , Vincent Gavin , Tadhg Creedon , Suzanne M Hughes , Mike Lardner , Padraic O'Reilly
IPC分类号： H03K300
CPC分类号： G06F5/06 , G06F1/12
摘要： A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.
摘要翻译：芯片系统的时钟方案，其中系统时钟的积分子倍数在系统时钟的奇数正边缘上具有正边沿，在偶数正边缘上具有负边沿在不同频率的块之间的数据传输由高频块的状态机，并且可以在没有弹性缓冲器和/或同步器的情况下实现。

5. 发明申请

US20120150527A1 STORAGE PERIPHERAL DEVICE EMULATION 审中-公开
标题翻译：存储外围设备仿真
公开(公告)号：US20120150527A1
公开(公告)日：2012-06-14
申请号：US13390787
申请日：2010-08-20
申请人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
发明人： Tadhg Creedon , Vincent Gavin , Eugene McCabe
IPC分类号： G06F9/455
CPC分类号： G06F3/0632 , G06F3/0607 , G06F3/0683
摘要： An emulation system (1) comprises a programming system (2) made up of a laptop computer (2(a)) and a central server (2(b)), an interrogation station (3), and a programmable storage peripheral device (4). The system (1) links with an existing disk storage peripheral device (10) to retrieve characterisation data, and upload it to the central server (2(b)). The laptop computer (2(a)) then retrieves the characterization data and then programs the programmable device (4) to emulate the full functionality of the pre-existing computer storage peripheral (10). The device (4) is programmed by the host computer (2) to fully replicate characteristics including electrical and timing characteristics and command responses. The programmable device (4) does not have a disk drive, the only storage components being solid state non-volatile memory components, in this embodiment flash memory and volatile components including DRAM. The flash components include mostly NAND flash, but also NOR flash.
摘要翻译：仿真系统（1）包括由膝上型计算机（2（a））和中央服务器（2（b））组成的编程系统（2），询问站（3）和可编程存储外围设备 4）。系统（1）与现有的磁盘存储外围设备（10）链接以检索表征数据，并将其上传到中央服务器（2（b））。膝上型计算机（2（a））然后检索表征数据，然后对可编程设备（4）进行编程，以模拟预先存在的计算机存储外围设备（10）的全部功能。设备（4）由主计算机（2）编程，以完全复制包括电气和定时特性以及命令响应的特性。可编程器件（4）没有磁盘驱动器，唯一的存储组件是固态非易失性存储器组件，在这个实施例中，闪速存储器和包括DRAM的易失性组件。闪存组件主要包括NAND闪存，也包括NOR闪存。

6. 发明授权

US06877145B2 Automatic generation of interconnect logic components 有权
标题翻译：自动生成互连逻辑元件
公开(公告)号：US06877145B2
公开(公告)日：2005-04-05
申请号：US09919806
申请日：2001-08-02
申请人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
发明人： Sean Boylan , Derek Coburn , Tadhg Creedon , Denise De Paor , Vincent Gavin , Kevin J Hyland , Suzanne M Hughes , Kevin Jennings , Mike Lardner , Brendan Walsh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
摘要翻译：自动生成片上系统的互连逻辑的程序工具基于运行核心库和需要核心之间的所有数据交换的架构，通过可能是“片外”的共享存储器进行。该架构包括用于具有连续级别的仲裁来访问存储器的数据聚合技术。

7. 发明授权

US06684258B1 Stackable ring network including burst transmission of data packet 失效
标题翻译：可堆叠环网包括数据包的突发传输
公开(公告)号：US06684258B1
公开(公告)日：2004-01-27
申请号：US09547759
申请日：2000-04-12
申请人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
发明人： Vincent Gavin , Una Quinlan , Denise De Paor , Tadhg Creedon , Nicholas M Stapleton
IPC分类号： G06F1516
CPC分类号： H04L12/433
摘要： A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration. The master unit indicates the nature of the subsequent packet by setting a sequence number in the header of the packet to distinguish it and following packets in a burst from the ‘first’ packet which is the one used to pick up requests from the units that may need to become the master unit.
摘要翻译：可以与其他单元形成环的可堆叠网络单元具有主模式，其中它可以在环上放置分组，使得它们可以最终从其他单元转发，并且可以在其中进行转移请求的重复模式在该仲裁包的头部插入位。如果主单元已经完成了分组的传输，并且优选地，在所需的分组间间隔已经过去之后，它还没有接收到仲裁报头以允许作出可以发送后续分组的仲裁决定。该分组的报头信息向其他单元指示该后续分组是分组的突发的一部分，并且其他单元不应该在该分组的报头中设置请求，因为该分组不会用于仲裁。主单元通过在分组报头中设置序列号来指示后续分组的性质，以便从“第一”分组中突发出来的分组中跟随分组，该分组是用于从可能的单元接收请求的分组需要成为主机。

8. 发明授权

US07076600B2 Dual purpose interface using refresh cycle 失效
标题翻译：双用途界面使用刷新循环
公开(公告)号：US07076600B2
公开(公告)日：2006-07-11
申请号：US10267826
申请日：2002-10-10
申请人： Vincent Gavin
发明人： Vincent Gavin
IPC分类号： G06F12/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C11/406
摘要： A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh the shared signal paths include at least some of the address and data signal paths.
摘要翻译：一种用于优化DRAM接口上的信号路径的使用的方法和系统。在DRAM刷新期间具有“不关心”状态的信号路径被分配给与另一设备的通信。刷新过程的开始在共享信号路径的持续时间期间触发共享信号路径从DRAM移动到另一个设备，包括至少一些地址和数据信号路径。

9. 发明授权

US06718411B2 Asic system architecture including data aggregation technique 失效
标题翻译： Asic系统架构包括数据聚合技术
公开(公告)号：US06718411B2
公开(公告)日：2004-04-06
申请号：US09893659
申请日：2001-06-29
申请人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
发明人： Tadhg Creedon , Vincent Gavin , Denise de Paor , Kevin J Hyland , Kevin Jennings , Derek Coburn , Mike Lardner , Suzanne M Hughes , Sean Boylan , Brendan Walsh
IPC分类号： G06F1336
CPC分类号： G06F17/5045
摘要： An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.
摘要翻译：一种用于芯片上系统的架构，其中功能核心具有用于与公共总线系统兼容的封装器，并且总线系统包括用于不同速度和/或总线宽度的总线事务的聚合器。

10. 发明授权

US06625684B1 Application specific integrated circuit with dual-mode system for externally accessible data buses and visibility buses 失效
标题翻译：具有双模系统的专用集成电路，用于外部可访问的数据总线和可见性总线
公开(公告)号：US06625684B1
公开(公告)日：2003-09-23
申请号：US09668301
申请日：2000-09-25
申请人： Fergus Casey , Vincent Gavin , Gareth E Allwright , Kam Choi , Christopher Hay , Kevin Loughran , Patrick Gibson
发明人： Fergus Casey , Vincent Gavin , Gareth E Allwright , Kam Choi , Christopher Hay , Kevin Loughran , Patrick Gibson
IPC分类号： G06F1300
CPC分类号： G06F11/267 , G01R31/318505
摘要： An application specific integrated circuit includes a multiplicity of operational blocks each of which includes at least one respective data bus and at least one respective visibility bus and a respective addressable multiplexer for selecting between those buses to provide an output on a to respective block bus. An interface block includes a first addressable multiplexer for selecting output data from a selected one of the blocks and providing an output; a register coupled to the output of the first addressable multiplexer; and a second addressable multiplexer for selecting between data provided by the output of the first addressable multiplexer and data in the register. Different portions of externally supplied address words are applied to the first addressable multiplexer and the respective addressable multiplexer, and a decoder is responsive to the address words for controlling the second addressable multiplexer. The arrangement provides a common multiplexing system for data buses and visibility buses.
摘要翻译：专用集成电路包括多个操作块，每个操作块包括至少一个相应的数据总线和至少一个相应的可见性总线和相应的可寻址复用器，用于在这些总线之间选择以在相应的模块总线上提供输出。接口块包括第一可寻址复用器，用于从所选择的一个块中选择输出数据并提供输出; 耦合到第一可寻址复用器的输出的寄存器; 以及第二可寻址复用器，用于在由第一可寻址多路复用器的输出提供的数据和寄存器中的数据之间进行选择。外部提供的地址字的不同部分被应用于第一可寻址复用器和相应的可寻址复用器，并且解码器响应于地址字来控制第二可寻址多路复用器。该装置为数据总线和可视化总线提供了一个共同的多路复用系统。

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