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1. 发明授权

US06728745B1 Semiconductor circuit for arithmetic operation and method of arithmetic operation 失效
标题翻译：用于算术运算的半导体电路和算术运算方法
公开(公告)号：US06728745B1
公开(公告)日：2004-04-27
申请号：US09581729
申请日：2000-09-06
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F750
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于在计算时间单元内计算输入数据的计算单元，并且输出表示通过计算得到的结果的计算结果，并且如果在计算中产生进位，则用于输出进位数据的计算电路（加法器1-3）并且提供用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

2. 发明授权

US07296048B2 Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
标题翻译：用于算术处理和算术处理方法的半导体电路
公开(公告)号：US07296048B2
公开(公告)日：2007-11-13
申请号：US10641788
申请日：2003-08-15
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F7/52
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing.There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1–3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

3. 发明申请

US20050080835A1 Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
标题翻译：用于算术处理和算术处理方法的半导体电路
公开(公告)号：US20050080835A1
公开(公告)日：2005-04-14
申请号：US10641788
申请日：2003-08-15
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F7/00 , G06F7/48 , G06F7/50 , G06F7/506
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

4. 发明授权

US06456532B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06456532B1
公开(公告)日：2002-09-24
申请号：US09673546
申请日：2001-02-07
申请人： Tadahiro Ohmi , Tadashi Shibata , Keng Hoong Wee , Takemi Yonezawa , Toshiyuki Nozawa , Takahisa Nitta
发明人： Tadahiro Ohmi , Tadashi Shibata , Keng Hoong Wee , Takemi Yonezawa , Toshiyuki Nozawa , Takahisa Nitta
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C27/005 , G11C2211/5613
摘要： The present invention is intended to provide a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy. The semiconductor memory circuit comprises a memory cell in which analog and many-valued signals can be written and stored, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparator having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals to a predetermined voltage, a write voltage controlling circuit having an output terminal which outputs an output voltage corresponding to the analog and many-valued voltage values inputted to an input terminal as a writing voltage of the memory cell, and a write voltage switching circuit having a function which supplies the output voltage of the write voltage controlling circuit to the memory cell and stops to supply the output voltage of the write voltage controlling circuit to the memory cell when the write end signal is outputted to the output terminal of the comparator.
摘要翻译：本发明旨在提供一种半导体存储器电路，其可以以高速度和高精度存储模拟和多值数据。半导体存储器电路包括其中可以写入和存储模拟和多值信号的存储单元，具有输出端子的读出电路，其输出存储在存储器单元中的值作为电压;比较器，具有输出端子当读出电路的输出端子电压等于预定电压时，该输出端输出写入结束信号;写入电压控制电路，具有输出端子，该输出端子输出对应于模拟的输出电压和输入到输入端子的多值电压值作为存储单元的写入电压，以及具有将写入电压控制电路的输出电压提供给存储单元并停止以将写入电压控制电路的输出电压提供给存储单元的功能的写入电压切换电路当写入结束信号被输出到比较器的输出端时。

5. 发明授权

US5917742A Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US5917742A
公开(公告)日：1999-06-29
申请号：US806744
申请日：1997-02-27
申请人： Tadahiro Ohmi , Makoto Imai , Koji Kotani , Tadashi Shibata
发明人： Tadahiro Ohmi , Makoto Imai , Koji Kotani , Tadashi Shibata
IPC分类号： G06F7/509 , G06F7/49 , G06F7/501 , G06G7/14 , H01L27/10 , H03K19/20 , H03M1/00 , G06G7/00 , G06F7/00
CPC分类号： G06F7/49
摘要： A semiconductor arithmetic circuit which realizes multiple-item addition processing at high speed and with a small surface areas The semiconductor arithmetic circuit adds a plurality of data expressed in binary format which is provided with terminals for the simultaneous input of the plurality of data, a mechanism for conducting a batch addition operation with respect to all the bits of the plurality of data, and for generating an analog or multi-valued signal having a linear relationship with the results of this addition and a mechanism for converting the analog or multi-valued signal to a digital signal. The plurality of data comprise bit data signals, and 4 or more of these are subjected to batch addition. A plurality of bit groups including a plurality of connected bits are also subjected to batch addition.
摘要翻译：一种半导体运算电路，其以高速实现多项目相加处理并具有小的表面积半导体运算电路将多个以二进制格式表示的数据相加，该多个数据被提供有用于同时输入多个数据的终端，用于针对所述多个数据的所有位执行批量添加操作，并且用于生成与该相加结果具有线性关系的模拟或多值信号以及用于转换模拟或多值信号的机制到数字信号。多个数据包括比特数据信号，其中4个或更多个进行批量添加。包括多个连接的位的多个位组也被进行批量添加。

6. 发明授权

US6150851A Charge transfer amplifier circuit, voltage comparator, and sense amplifier 失效
标题翻译：电荷传输放大器电路，电压比较器和读出放大器
公开(公告)号：US6150851A
公开(公告)日：2000-11-21
申请号：US92465
申请日：1998-06-05
申请人： Tadahiro Ohmi , Takahisa Nitta , Koji Kotani
发明人： Tadahiro Ohmi , Takahisa Nitta , Koji Kotani
IPC分类号： G01R19/165 , G11C27/02 , H03K5/08
CPC分类号： G11C27/026
摘要： Charge transfer amplifier circuit which is capable of canceling fluctuations in the element characteristics thereof and which conducts highly accurate voltage amplification without the use of a stationary current, and provides a voltage comparator which may be applied to a highly accurate A/D converter which has low power consumption. The charge transfer amplifier circuit is provided with a MOS transistor, a first capacity and a second capacity which are effectively connected to, respectively, the source electrode and the drain electrode of the MOS transistor, a mechanism for setting the region between the terminals of the first capacity and the region between the terminals of the second capacity, respectively, to appropriate predetermined potential differences, and for releasing these, and a mechanism for appropriately externally altering the potential difference between the gate and the source of the MOS transistor. The first capacity is set so as to be larger than the second capacity. Furthermore, in the voltage comparator, a dynamic latch circuit is connected to the drain electrode of the charge transfer amplifier circuit.
摘要翻译：电荷传输放大器电路，其能够抵消其元件特性的波动，并且在不使用稳定电流的情况下进行高精度的电压放大，并且提供可应用于具有低电平的高精度A / D转换器的电压比较器能量消耗。电荷传输放大器电路设置有分别有效地连接到MOS晶体管的源电极和漏电极的MOS晶体管，第一电容和第二电容，用于设置MOS晶体管的端子之间的区域的机构第一容量和第二容量的端子之间的区域分别适当地预定的电位差，并且用于释放它们，以及用于适当地外部改变MOS晶体管的栅极和源极之间的电位差的机构。第一容量被设定为大于第二容量。此外，在电压比较器中，动态锁存电路连接到电荷传输放大器电路的漏电极。

7. 发明授权

US06704757B1 Semiconductor arithmetic unit 失效
标题翻译：半导体运算单元
公开(公告)号：US06704757B1
公开(公告)日：2004-03-09
申请号：US09673516
申请日：2001-01-02
申请人： Tadahiro Ohmi , Tadashi Shibata , Akira Nakada , Tatsuro Morimoto , Takahisa Nitta
发明人： Tadahiro Ohmi , Tadashi Shibata , Akira Nakada , Tatsuro Morimoto , Takahisa Nitta
IPC分类号： G06J100
CPC分类号： G06N3/063 , G06N3/0635
摘要： A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group. The second amplifying circuit includes an adjusting circuit which adjusts an output current driving ability and a controlling circuit which controls the adjustment with a predetermined regulation. The adjustment of the controlling circuit is executed according to variation of the output of the logical operation circuit.
摘要翻译：实现在矢量量化处理器中使用的高速度和高精度的最大值或最小值检索操作的半导体运算单元由二进制多值模拟合并运算处理电路构成。多回路电路包括由具有浮置栅极的多组第一放大器组成的放大电路组，第一电极和单个第二电极以预定比率电容耦合到该第一放大器;逻辑运算电路，输入逻辑0或1的放大电路组，输入逻辑运算电路的输出信号并将其输出分配给放大电路组的所有第二电极的第二放大电路。第二放大电路包括调节输出电流驱动能力的调节电路和控制电路，控制电路以预定的调节进行调节。控制电路的调整根据逻辑运算电路的输出的变化进行。

8. 发明授权

US06199092B1 Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US06199092B1
公开(公告)日：2001-03-06
申请号：US09158244
申请日：1998-09-22
申请人： Tadashi Shibata , Akira Nakada , Masahiro Konnda , Tadahiro Ohmi , Takahisa Nitta
发明人： Tadashi Shibata , Akira Nakada , Masahiro Konnda , Tadahiro Ohmi , Takahisa Nitta
IPC分类号： G06G700
CPC分类号： G06G7/14
摘要： A semiconductor arithmetic circuit including 2 MOS (Metal Oxide Semiconductor) type transistors, the source electrodes of which are connected to one another and having gate electrodes connected to a signal line having a predetermined potential via switching elements, and having at least two input electrodes capacitively coupled with the gate electrodes, wherein a first voltage and second voltage are applied to, respectively, a first and second input electrode of a first MOS transistor. An input signal voltage is applied to both a first and second input electrode of a second MOS transistor, and then a second switching element is caused to conduct, and the gate electrodes are set to the signal line potential, then the second switching element is isolated and the gate electrodes are placed in an electrically floating state. The first voltage and the second voltage are inputted into, respectively, the first and second input electrodes of the second MOS type transistor, and the input signal voltage is inputted into the first and second input electrodes of the first MOS transistor, and thereby, the absolute value of the difference between a voltage determined in accordance with the first voltage and the second voltage and a coupling capacity ratio between the first and the second input electrodes with respect to the gate electrode, and a voltage determined by the input signal voltage and the coupling capacity ratio is calculated.
摘要翻译：一种半导体运算电路，包括2个MOS（金属氧化物半导体）型晶体管，其源极彼此连接并且具有通过开关元件连接到具有预定电位的信号线的栅电极，并且具有至少两个输入电极电容与栅电极耦合，其中第一电压和第二电压分别施加到第一MOS晶体管的第一和第二输入电极。输入信号电压施加到第二MOS晶体管的第一和第二输入电极，然后使第二开关元件导通，并且将栅电极设置为信号线电位，然后隔离第二开关元件并且栅电极被置于电浮动状态。第一电压和第二电压分别输入到第二MOS型晶体管的第一和第二输入电极，并且输入信号电压被输入到第一MOS晶体管的第一和第二输入电极中，从而，根据第一电压和第二电压确定的电压与第一和第二输入电极之间的相对于栅电极的耦合容量比的差的绝对值，以及由输入信号电压和计算耦合容量比。

9. 发明授权

US5959484A Feed back circuit 失效
标题翻译：回馈电路
公开(公告)号：US5959484A
公开(公告)日：1999-09-28
申请号：US807374
申请日：1997-02-27
申请人： Tadahiro Ohmi , Tadashi Shibata , Hiroaki Terada , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Hiroaki Terada , Koji Kotani
IPC分类号： G06G7/60 , H01L21/8234 , H01L27/088 , H03K3/356 , H03K19/08 , H03K19/20
CPC分类号： H03K19/0813
摘要： A feedback circuit is provided which is capable of realizing handshake functions, flip flop functions, and other functions using a smaller number of elements and chip surface. The threshold circuit is provided with an electrode which is electrically floating and a plurality of input electrodes which are connected with the floating electrode via capacity elements, and the circuit has a mechanism for essentially determining the potential of the floating electrode by means of the potentials applied to the input electrodes, and the output of the circuit is determined by the potential of the floating gate; the output of the threshold circuit is connected to at least one of the plurality of input electrodes, either directly, or via at least one circuit of some type.
摘要翻译：提供了一种反馈电路，其能够使用较少数量的元件和芯片表面来实现握手功能，触发器功能和其他功能。阈值电路设置有电浮动的电极和通过电容元件与浮动电极连接的多个输入电极，并且电路具有用于通过施加的电位基本上确定浮置电极的电位的机构到输入电极，并且电路的输出由浮栅的电位确定; 阈值电路的输出直接或经由某种类型的至少一个电路连接到多个输入电极中的至少一个。

10. 发明授权

US5661421A Semiconductor integrated data matching circuit 失效
标题翻译：半导体集成数据匹配电路
公开(公告)号：US5661421A
公开(公告)日：1997-08-26
申请号：US507473
申请日：1995-09-29
申请人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
IPC分类号： G06F7/04 , G06G7/60 , G06N3/063 , H03K19/21 , A03K5/22
CPC分类号： G06N3/0635
摘要： A semiconductor integrated circuit for effecting data matching at high speed is provided in a simple circuit. The semiconductor integrated circuit includes a first input terminal and a second input terminal to which first and second voltage signals representing first and second values are inputted, respectively, and an output terminal. A predetermined output signal is produced at the output terminal when the difference between the first and second values is smaller than a predetermined difference value. The semiconductor integrated circuit of this invention comprises first and second inverters, each inverter comprising neuron MOS transistors having a plurality of input gates. The first and second signals or, first and second processed signals obtained by applying predetermined processing to the first and second signals, are inputted to at least one of the input gates of the inverters.
摘要翻译： PCT No.PCT / JP94 / 00263 Sec。 371 1995年9月29日第 102（e）1995年9月29日PCT PCT 1994年2月22日PCT公布。 WO94 / 19761 PCT出版物日期1994年9月1日在简单的电路中提供用于高速实现数据匹配的半导体集成电路。半导体集成电路包括分别输入表示第一和第二值的第一和第二电压信号的第一输入端和第二输入端和输出端。当第一和第二值之间的差小于预定的差值时，在输出端产生预定的输出信号。本发明的半导体集成电路包括第一和第二反相器，每个反相器包括具有多个输入门的神经元MOS晶体管。通过对第一和第二信号应用预定处理而获得的第一和第二信号或第一和第二处理信号被输入至反相器的至少一个输入门。

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