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1. 发明授权

US5959484A Feed back circuit 失效
标题翻译：回馈电路
公开(公告)号：US5959484A
公开(公告)日：1999-09-28
申请号：US807374
申请日：1997-02-27
申请人： Tadahiro Ohmi , Tadashi Shibata , Hiroaki Terada , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Hiroaki Terada , Koji Kotani
IPC分类号： G06G7/60 , H01L21/8234 , H01L27/088 , H03K3/356 , H03K19/08 , H03K19/20
CPC分类号： H03K19/0813
摘要： A feedback circuit is provided which is capable of realizing handshake functions, flip flop functions, and other functions using a smaller number of elements and chip surface. The threshold circuit is provided with an electrode which is electrically floating and a plurality of input electrodes which are connected with the floating electrode via capacity elements, and the circuit has a mechanism for essentially determining the potential of the floating electrode by means of the potentials applied to the input electrodes, and the output of the circuit is determined by the potential of the floating gate; the output of the threshold circuit is connected to at least one of the plurality of input electrodes, either directly, or via at least one circuit of some type.
摘要翻译：提供了一种反馈电路，其能够使用较少数量的元件和芯片表面来实现握手功能，触发器功能和其他功能。阈值电路设置有电浮动的电极和通过电容元件与浮动电极连接的多个输入电极，并且电路具有用于通过施加的电位基本上确定浮置电极的电位的机构到输入电极，并且电路的输出由浮栅的电位确定; 阈值电路的输出直接或经由某种类型的至少一个电路连接到多个输入电极中的至少一个。

2. 发明授权

US5661421A Semiconductor integrated data matching circuit 失效
标题翻译：半导体集成数据匹配电路
公开(公告)号：US5661421A
公开(公告)日：1997-08-26
申请号：US507473
申请日：1995-09-29
申请人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
IPC分类号： G06F7/04 , G06G7/60 , G06N3/063 , H03K19/21 , A03K5/22
CPC分类号： G06N3/0635
摘要： A semiconductor integrated circuit for effecting data matching at high speed is provided in a simple circuit. The semiconductor integrated circuit includes a first input terminal and a second input terminal to which first and second voltage signals representing first and second values are inputted, respectively, and an output terminal. A predetermined output signal is produced at the output terminal when the difference between the first and second values is smaller than a predetermined difference value. The semiconductor integrated circuit of this invention comprises first and second inverters, each inverter comprising neuron MOS transistors having a plurality of input gates. The first and second signals or, first and second processed signals obtained by applying predetermined processing to the first and second signals, are inputted to at least one of the input gates of the inverters.
摘要翻译： PCT No.PCT / JP94 / 00263 Sec。 371 1995年9月29日第 102（e）1995年9月29日PCT PCT 1994年2月22日PCT公布。 WO94 / 19761 PCT出版物日期1994年9月1日在简单的电路中提供用于高速实现数据匹配的半导体集成电路。半导体集成电路包括分别输入表示第一和第二值的第一和第二电压信号的第一输入端和第二输入端和输出端。当第一和第二值之间的差小于预定的差值时，在输出端产生预定的输出信号。本发明的半导体集成电路包括第一和第二反相器，每个反相器包括具有多个输入门的神经元MOS晶体管。通过对第一和第二信号应用预定处理而获得的第一和第二信号或第一和第二处理信号被输入至反相器的至少一个输入门。

3. 发明授权

US07296048B2 Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
标题翻译：用于算术处理和算术处理方法的半导体电路
公开(公告)号：US07296048B2
公开(公告)日：2007-11-13
申请号：US10641788
申请日：2003-08-15
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F7/52
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing.There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1–3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

4. 发明申请

US20050080835A1 Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
标题翻译：用于算术处理和算术处理方法的半导体电路
公开(公告)号：US20050080835A1
公开(公告)日：2005-04-14
申请号：US10641788
申请日：2003-08-15
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F7/00 , G06F7/48 , G06F7/50 , G06F7/506
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

5. 发明授权

US5682109A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5682109A
公开(公告)日：1997-10-28
申请号：US600760
申请日：1996-02-13
申请人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063 , G11C11/54 , H03K3/356 , H03K19/20 , G01R19/00
CPC分类号： H03K3/356139 , H03K3/356104
摘要： The present invention relates to a semiconductor integrated circuit. In greater detail, the present invention relates to a semiconductor integrated circuit which conducts calculations using a voltage adding function by means of capacity and threshold operations. The semiconductor integrated circuit in accordance with the present invention is characterized in that, in a circuit wherein the output of a first inverter circuit and the input of a second inverter circuit are connected at a first contact point, the output of the second inverter and the input of the first inverter are connected at a second contact point, and a means is provided for generating a difference in potential between the first contact point and the second contact point, an electrically floating electrode and a plurality of input electrodes, which are provided via capacity elements with this electrode, are provided, and a means is provided for in effect determining the difference in potential by means of the potentials applied to the input electrodes.
摘要翻译：半导体集成电路技术领域本发明涉及半导体集成电路。更详细地说，本发明涉及利用容量和阈值操作使用加电功能进行计算的半导体集成电路。根据本发明的半导体集成电路的特征在于，在第一反相器电路的输出和第二反相器电路的输入在第一接触点处连接的电路中，第二反相器的输出和第一反相器的输入端连接在第二接触点处，并且提供用于产生第一接触点和第二接触点之间的电位差的装置，电浮动电极和多个输入电极，其经由提供了具有该电极的电容元件，并且提供了用于通过施加到输入电极的电位实际上确定电位差的装置。

6. 发明授权

US5937399A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5937399A
公开(公告)日：1999-08-10
申请号：US663248
申请日：1996-06-11
申请人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
IPC分类号： G06F15/18 , G06N3/063 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06N3/0635
摘要： A semiconductor integrated circuit includes one or more neuron MOS transistors on a substrate. The MOS transistor comprises a semiconductor region of one conductivity type, source and drain regions of opposite conductivity type disposed in this region, floating gate disposed on an insulating film between the source and drain regions, and a plurality of input coupling electrodes making capacitive coupling with the floating gate through the insulating film, wherein the floating gate is connected to at least one switching device.
摘要翻译： PCT No.PCT / JP94 / 02001 Sec。 371日期：1996年6月11日 102（e）日期1996年6月11日PCT 1994年11月29日PCT公布。第WO95 / 15581号公报日期：1995年6月8日半导体集成电路在衬底上包括一个或多个神经元MOS晶体管。 MOS晶体管包括一个导电类型的半导体区域，设置在该区域中的具有相反导电类型的源极和漏极区域，浮置栅极设置在源极和漏极区域之间的绝缘膜上，以及多个输入耦合电极，所述浮栅通过所述绝缘膜，其中所述浮动栅极连接到至少一个开关装置。

7. 发明授权

US06728745B1 Semiconductor circuit for arithmetic operation and method of arithmetic operation 失效
标题翻译：用于算术运算的半导体电路和算术运算方法
公开(公告)号：US06728745B1
公开(公告)日：2004-04-27
申请号：US09581729
申请日：2000-09-06
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F750
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于在计算时间单元内计算输入数据的计算单元，并且输出表示通过计算得到的结果的计算结果，并且如果在计算中产生进位，则用于输出进位数据的计算电路（加法器1-3）并且提供用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

8. 发明授权

US5917742A Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US5917742A
公开(公告)日：1999-06-29
申请号：US806744
申请日：1997-02-27
申请人： Tadahiro Ohmi , Makoto Imai , Koji Kotani , Tadashi Shibata
发明人： Tadahiro Ohmi , Makoto Imai , Koji Kotani , Tadashi Shibata
IPC分类号： G06F7/509 , G06F7/49 , G06F7/501 , G06G7/14 , H01L27/10 , H03K19/20 , H03M1/00 , G06G7/00 , G06F7/00
CPC分类号： G06F7/49
摘要： A semiconductor arithmetic circuit which realizes multiple-item addition processing at high speed and with a small surface areas The semiconductor arithmetic circuit adds a plurality of data expressed in binary format which is provided with terminals for the simultaneous input of the plurality of data, a mechanism for conducting a batch addition operation with respect to all the bits of the plurality of data, and for generating an analog or multi-valued signal having a linear relationship with the results of this addition and a mechanism for converting the analog or multi-valued signal to a digital signal. The plurality of data comprise bit data signals, and 4 or more of these are subjected to batch addition. A plurality of bit groups including a plurality of connected bits are also subjected to batch addition.
摘要翻译：一种半导体运算电路，其以高速实现多项目相加处理并具有小的表面积半导体运算电路将多个以二进制格式表示的数据相加，该多个数据被提供有用于同时输入多个数据的终端，用于针对所述多个数据的所有位执行批量添加操作，并且用于生成与该相加结果具有线性关系的模拟或多值信号以及用于转换模拟或多值信号的机制到数字信号。多个数据包括比特数据信号，其中4个或更多个进行批量添加。包括多个连接的位的多个位组也被进行批量添加。

9. 发明授权

US08551830B2 Semiconductor integrated circuit switch matrix 有权
标题翻译：半导体集成电路开关矩阵
公开(公告)号：US08551830B2
公开(公告)日：2013-10-08
申请号：US12110800
申请日：2008-04-28
申请人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L27/12 , H01L21/8221 , H01L27/0688 , Y10S257/903
摘要： There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.
摘要翻译：提供电路面积小，布线长度短的小型半导体集成电路。半导体集成电路构造为多层结构，并且设置有第一半导体层，形成在第一半导体层中的第一半导体层晶体管，布置在第一半导体层上并且其中金属线为形成，沉积在布线层上的第二半导体层和形成在第二半导体层中的第二半导体层晶体管。注意，第一半导体层晶体管的栅极绝缘膜的绝缘几乎等于第二半导体层晶体管的栅极绝缘膜的绝缘，并且通过自由基氧化形成第二半导体层晶体管的栅极绝缘膜或自由基氮化。

10. 发明授权

US07566936B2 Complementary MIS device 失效
标题翻译：互补MIS设备
公开(公告)号：US07566936B2
公开(公告)日：2009-07-28
申请号：US11606181
申请日：2006-11-30
申请人： Tadahiro Ohmi , Koji Kotani , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Koji Kotani , Shigetoshi Sugawa
IPC分类号： H01L29/76
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L27/092 , H01L27/0922 , H01L29/66795 , H01L29/7851
摘要： A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode formed thereon, wherein the size and the shape of the foregoing structure is set such that the carrier mobility is balanced between the p-channel MOS transistor and the n-channel MOS transistor.
摘要翻译： CMOS器件包括具有形成在硅衬底（100）表面上并具有不同晶体表面的结构的p沟道MOS晶体管和n沟道MOS晶体管，形成在这种结构上的高质量栅极绝缘膜通过微波等离子体处理和形成在其上的栅电极，其中上述结构的尺寸和形状被设置为使得载流子迁移率在p沟道MOS晶体管和n沟道MOS晶体管之间平衡。

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