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1. 发明授权

US06704757B1 Semiconductor arithmetic unit 失效
标题翻译：半导体运算单元
公开(公告)号：US06704757B1
公开(公告)日：2004-03-09
申请号：US09673516
申请日：2001-01-02
申请人： Tadahiro Ohmi , Tadashi Shibata , Akira Nakada , Tatsuro Morimoto , Takahisa Nitta
发明人： Tadahiro Ohmi , Tadashi Shibata , Akira Nakada , Tatsuro Morimoto , Takahisa Nitta
IPC分类号： G06J100
CPC分类号： G06N3/063 , G06N3/0635
摘要： A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group. The second amplifying circuit includes an adjusting circuit which adjusts an output current driving ability and a controlling circuit which controls the adjustment with a predetermined regulation. The adjustment of the controlling circuit is executed according to variation of the output of the logical operation circuit.
摘要翻译：实现在矢量量化处理器中使用的高速度和高精度的最大值或最小值检索操作的半导体运算单元由二进制多值模拟合并运算处理电路构成。多回路电路包括由具有浮置栅极的多组第一放大器组成的放大电路组，第一电极和单个第二电极以预定比率电容耦合到该第一放大器;逻辑运算电路，输入逻辑0或1的放大电路组，输入逻辑运算电路的输出信号并将其输出分配给放大电路组的所有第二电极的第二放大电路。第二放大电路包括调节输出电流驱动能力的调节电路和控制电路，控制电路以预定的调节进行调节。控制电路的调整根据逻辑运算电路的输出的变化进行。

2. 发明授权

US06199092B1 Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US06199092B1
公开(公告)日：2001-03-06
申请号：US09158244
申请日：1998-09-22
申请人： Tadashi Shibata , Akira Nakada , Masahiro Konnda , Tadahiro Ohmi , Takahisa Nitta
发明人： Tadashi Shibata , Akira Nakada , Masahiro Konnda , Tadahiro Ohmi , Takahisa Nitta
IPC分类号： G06G700
CPC分类号： G06G7/14
摘要： A semiconductor arithmetic circuit including 2 MOS (Metal Oxide Semiconductor) type transistors, the source electrodes of which are connected to one another and having gate electrodes connected to a signal line having a predetermined potential via switching elements, and having at least two input electrodes capacitively coupled with the gate electrodes, wherein a first voltage and second voltage are applied to, respectively, a first and second input electrode of a first MOS transistor. An input signal voltage is applied to both a first and second input electrode of a second MOS transistor, and then a second switching element is caused to conduct, and the gate electrodes are set to the signal line potential, then the second switching element is isolated and the gate electrodes are placed in an electrically floating state. The first voltage and the second voltage are inputted into, respectively, the first and second input electrodes of the second MOS type transistor, and the input signal voltage is inputted into the first and second input electrodes of the first MOS transistor, and thereby, the absolute value of the difference between a voltage determined in accordance with the first voltage and the second voltage and a coupling capacity ratio between the first and the second input electrodes with respect to the gate electrode, and a voltage determined by the input signal voltage and the coupling capacity ratio is calculated.
摘要翻译：一种半导体运算电路，包括2个MOS（金属氧化物半导体）型晶体管，其源极彼此连接并且具有通过开关元件连接到具有预定电位的信号线的栅电极，并且具有至少两个输入电极电容与栅电极耦合，其中第一电压和第二电压分别施加到第一MOS晶体管的第一和第二输入电极。输入信号电压施加到第二MOS晶体管的第一和第二输入电极，然后使第二开关元件导通，并且将栅电极设置为信号线电位，然后隔离第二开关元件并且栅电极被置于电浮动状态。第一电压和第二电压分别输入到第二MOS型晶体管的第一和第二输入电极，并且输入信号电压被输入到第一MOS晶体管的第一和第二输入电极中，从而，根据第一电压和第二电压确定的电压与第一和第二输入电极之间的相对于栅电极的耦合容量比的差的绝对值，以及由输入信号电压和计算耦合容量比。

3. 发明授权

US07296048B2 Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
标题翻译：用于算术处理和算术处理方法的半导体电路
公开(公告)号：US07296048B2
公开(公告)日：2007-11-13
申请号：US10641788
申请日：2003-08-15
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F7/52
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing.There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1–3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

4. 发明申请

US20050080835A1 Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
标题翻译：用于算术处理和算术处理方法的半导体电路
公开(公告)号：US20050080835A1
公开(公告)日：2005-04-14
申请号：US10641788
申请日：2003-08-15
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F7/00 , G06F7/48 , G06F7/50 , G06F7/506
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

5. 发明授权

US06456532B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06456532B1
公开(公告)日：2002-09-24
申请号：US09673546
申请日：2001-02-07
申请人： Tadahiro Ohmi , Tadashi Shibata , Keng Hoong Wee , Takemi Yonezawa , Toshiyuki Nozawa , Takahisa Nitta
发明人： Tadahiro Ohmi , Tadashi Shibata , Keng Hoong Wee , Takemi Yonezawa , Toshiyuki Nozawa , Takahisa Nitta
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C27/005 , G11C2211/5613
摘要： The present invention is intended to provide a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy. The semiconductor memory circuit comprises a memory cell in which analog and many-valued signals can be written and stored, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparator having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals to a predetermined voltage, a write voltage controlling circuit having an output terminal which outputs an output voltage corresponding to the analog and many-valued voltage values inputted to an input terminal as a writing voltage of the memory cell, and a write voltage switching circuit having a function which supplies the output voltage of the write voltage controlling circuit to the memory cell and stops to supply the output voltage of the write voltage controlling circuit to the memory cell when the write end signal is outputted to the output terminal of the comparator.
摘要翻译：本发明旨在提供一种半导体存储器电路，其可以以高速度和高精度存储模拟和多值数据。半导体存储器电路包括其中可以写入和存储模拟和多值信号的存储单元，具有输出端子的读出电路，其输出存储在存储器单元中的值作为电压;比较器，具有输出端子当读出电路的输出端子电压等于预定电压时，该输出端输出写入结束信号;写入电压控制电路，具有输出端子，该输出端子输出对应于模拟的输出电压和输入到输入端子的多值电压值作为存储单元的写入电压，以及具有将写入电压控制电路的输出电压提供给存储单元并停止以将写入电压控制电路的输出电压提供给存储单元的功能的写入电压切换电路当写入结束信号被输出到比较器的输出端时。

6. 发明授权

US06728745B1 Semiconductor circuit for arithmetic operation and method of arithmetic operation 失效
标题翻译：用于算术运算的半导体电路和算术运算方法
公开(公告)号：US06728745B1
公开(公告)日：2004-04-27
申请号：US09581729
申请日：2000-09-06
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F750
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于在计算时间单元内计算输入数据的计算单元，并且输出表示通过计算得到的结果的计算结果，并且如果在计算中产生进位，则用于输出进位数据的计算电路（加法器1-3）并且提供用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

7. 发明授权

US06462298B1 Long life welding electrode and its fixing structure, welding head and welding method 失效
标题翻译：长寿命焊接电极及其固定结构，焊头和焊接方法
公开(公告)号：US06462298B1
公开(公告)日：2002-10-08
申请号：US09045526
申请日：1998-03-20
申请人： Tadahiro Ohmi , Takahisa Nitta , Yasuyuki Shirai , Osamu Nakamura
发明人： Tadahiro Ohmi , Takahisa Nitta , Yasuyuki Shirai , Osamu Nakamura
IPC分类号： B23K3538
CPC分类号： B23K35/0205 , B23K9/28 , B23K35/222
摘要： The present invention provides a fixing structure for a welding electrode and a welding head which enable improvement of durability of a welding electrode, improvement of work efficiency in welding, and reduction of time required for welding and also which make it possible to execute welding for a long time with high reliability. In this fixing structure, a fixed section of a welding electrode is inserted via a thermally conductive material into an inserting section of a fixing base and a peripheral surface of the fixed section of the welding electrode is uniformly contacted to the fixing base to fix the welding electrode to the fixing base.
摘要翻译：本发明提供一种焊接电极和焊接头的固定结构，其能够提高焊接电极的耐久性，提高焊接中的工作效率，并且减少焊接所需的时间，并且还可以执行焊接长时间具有高可靠性。在该固定结构中，焊接电极的固定部分通过导热材料插入到固定基座的插入部分中，焊接电极的固定部分的周面与固定基座，将焊接电极固定在固定基座上。

8. 发明授权

US06416586B1 Cleaning method 有权
标题翻译：清洗方法
公开(公告)号：US06416586B1
公开(公告)日：2002-07-09
申请号：US09450167
申请日：1999-11-29
申请人： Tadahiro Ohmi , Toshihiro Il , Kenji Mori , Toshikazu Abe , Hirosi Arakawa , Takahisa Nitta
发明人： Tadahiro Ohmi , Toshihiro Il , Kenji Mori , Toshikazu Abe , Hirosi Arakawa , Takahisa Nitta
IPC分类号： B08B308
CPC分类号： H01L21/02052 , B08B3/08 , B08B3/123 , B08B2203/005 , Y10S134/902
摘要： The present invention has as an object thereof to provide a cleaning method which realizes, in the cleaning process, (1) a reduction in the number of processes, (2) a simplification of the cleaning apparatus, and (3) a reduction in the amount of chemicals and pure water employed, and which has highly superior cleaning effects and does not damage the substrate body, as well as to provide a rinsing method which aids in the hydrogen termination of silicon atoms.
摘要翻译：本发明的目的在于提供一种清洁方法，其在清洗过程中实现（1）减少加工次数，（2）清洁装置的简化，（3）减少使用的化学品和纯水的量，并且具有非常优异的清洁效果并且不会损坏基板主体，以及提供有助于硅原子的氢终止的冲洗方法。

9. 发明授权

US06348157B1 Cleaning method 失效
标题翻译：清洗方法
公开(公告)号：US06348157B1
公开(公告)日：2002-02-19
申请号：US09097278
申请日：1998-06-12
申请人： Tadahiro Ohmi , Takahisa Nitta , Kazuhiko Kawada , Mitsunori Nakamori , Toshihiro II
发明人： Tadahiro Ohmi , Takahisa Nitta , Kazuhiko Kawada , Mitsunori Nakamori , Toshihiro II
IPC分类号： H01L2100
CPC分类号： H01L21/02052 , B08B3/12 , Y10S438/906
摘要： A cleaning method capable of processing at room temperatures without conducting heating, uses little chemicals and water, and does not require special devices or materials. The chemical cleaning processes and rinse processes employ pure water or ultrapure water in a semiconductor wet cleaning process, rinse water or chemicals which suppresses formation of surface oxide films, removes particles and prevent their redeposition, and aids in the hydrogen termination of the silicon atoms. The cleaning method of the resent invention includes cleaning which is conducted using pure water containing ozone, cleaning conducted using a cleaning liquid containing HF, H2O, and surfactant, while applying vibration having a frequency of 500 kHz or more, cleaning conducted using pure water containing ozone, cleaning conducted using a cleaning liquid containing HF and H2O in order to remove oxide films, and cleaning which is conducted using pure water. After cleaning a material to be cleaned using chemicals, rinsing is conducted using pure water or ultrapure water containing hydrogen gas in an amount of 0.5 ppm or more and containing oxygen gas in an amount of 100 ppb or less.
摘要翻译：能够在不进行加热的情况下在室温下进行处理的清洁方法，使用少量化学物质和水，并且不需要特殊的装置或材料。化学清洗过程和漂洗工艺在半导体湿法清洗工艺中使用纯水或超纯水，冲洗水或抑制表面氧化膜形成的化学物质，去除颗粒并防止其再沉积，并有助于硅原子的氢终止。本发明的清洗方法包括使用含有臭氧的纯水进行的清洗，使用含有HF，H 2 O和表面活性剂的清洗液进行清洗，同时施加频率为500kHz以上的振动，使用含有臭氧，使用含有HF和H 2 O的清洗液进行清洁以除去氧化膜，以及使用纯水进行的清洗。在使用化学品清洁待清洁的材料之后，使用含有0.5ppm以上的氢气的纯水或超纯水进行冲洗，并含有100ppb以下的氧气。

10. 发明授权

US06325081B1 Washing apparatus and washing method 失效
标题翻译：洗衣机和洗涤方法
公开(公告)号：US06325081B1
公开(公告)日：2001-12-04
申请号：US09214240
申请日：1999-05-17
申请人： Nobuhiro Miki , Takahisa Nitta , Yasuyuki Harada , Tadahiro Ohmi
发明人： Nobuhiro Miki , Takahisa Nitta , Yasuyuki Harada , Tadahiro Ohmi
IPC分类号： B08B302
CPC分类号： H01L21/02052 , B08B3/02 , B08B2203/0288 , H01L21/67051
摘要： A washing apparatus and a washing method, which further improve a washing effect and enable highly clean washing with a small amount of chemical. Also, it is an object of the invention to provide a washing apparatus of high throughput involving rapid switching of various chemicals of high responsibility and capable of performing a series of washing operations at high speed. The washing apparatus comprises undiluted cleaning liquid injection means for injecting an undiluted solution or undiluted gas of a cleaning liquid into a ultrapure water channel to make a cleaning liquid of a desired concentration, cleaning liquid supplying means connected to the super demineralized water channel for simultaneously supplying front and rear surface of a substrate with a cleaning liquid adjusted to a desired concentration or a ultrapure water, means for superposing ultrasonic wave or high frequency sound waves of 0.5 MHz or more on the substrate through the cleaning liquid, and means for rotating the substrate or means for moving either of the substrate and the cleaning liquid supplying means in one direction, whereby injection of the undiluted solution or undiluted gas into the ultrapure water channel is controlled to continuously perform washing of the substrate by the cleaning liquid and washing by the ultrapure water.
摘要翻译：一种洗涤装置和洗涤方法，其进一步改善洗涤效果并且能够用少量化学品进行高度清洁的洗涤。另外，本发明的目的是提供一种高产量的洗涤装置，涉及快速切换各种高度责任的化学品，能够高速地进行一系列洗涤操作。洗涤装置包括未稀释的清洗液注入装置，将未稀释的溶液或清洁液体的未稀释气体输送到超纯水通道中以制备所需浓度的清洗液体，连接到超级软化水通道的清洗液供应装置，用于同时向基材的前表面和后表面提供清洁液体调节到期望浓度或超纯水的装置，用于通过清洁液体在衬底上叠加超声波或0.5MHz以上的高频声波的装置，以及用于旋转衬底或用于移动衬底和清洁装置的装置的装置液体供应装置在一个方向上，由此注射未稀释的控制溶液或未稀释气体进入超纯水通道，以通过清洗液体连续地进行基材清洗，并通过超纯水进行洗涤。

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