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1. 发明申请

US20070066007A1 Method to obtain fully silicided gate electrodes 有权
标题翻译：获得完全硅化栅电极的方法
公开(公告)号：US20070066007A1
公开(公告)日：2007-03-22
申请号：US11228902
申请日：2005-09-16
申请人： Steven Vitale , Hyesook Hong , Freidoon Mehrad
发明人： Steven Vitale , Hyesook Hong , Freidoon Mehrad
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823443 , H01L21/823835
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255). Source/drains are formed adjacent the gate electrodes 250 and through the remnant of the spacer material (415), and a metal is incorporated into the gate electrodes (250).
摘要翻译：本发明提供一种制造微电子器件的方法。在一个方面，该方法包括在位于栅电极（250）之间的间隔材料（415）和位于栅电极（250）之间的掺杂区域（255）之间沉积保护层（510），去除间隔物的一部分材料（415）和位于栅电极（250）上方的保护层（510）。间隔材料（415）的剩余部分保留在栅电极（250）的顶表面上方并且在掺杂区域（255）之上，并且保护层（510）的一部分保留在掺杂区域（255）上方。该方法还包括去除间隔物材料（415）的剩余部分以在栅电极（250）上形成间隔壁侧壁，露出栅电极（250）的顶表面，并留下间隔物材料（415）的残留物在掺杂区域（255）上。源极/漏极形成在栅电极250附近并且通过间隔物材料（415）的残留物，并且金属被结合到栅电极（250）中。

2. 发明授权

US07244642B2 Method to obtain fully silicided gate electrodes 有权
公开(公告)号：US07244642B2
公开(公告)日：2007-07-17
申请号：US11228902
申请日：2005-09-16
申请人： Steven A. Vitale , Hyesook Hong , Freidoon Mehrad
发明人： Steven A. Vitale , Hyesook Hong , Freidoon Mehrad
IPC分类号： H01L21/337 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/469 , H01L21/31
CPC分类号： H01L21/823425 , H01L21/823443 , H01L21/823835
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255). Source/drains are formed adjacent the gate electrodes 250 and through the remnant of the spacer material (415), and a metal is incorporated into the gate electrodes (250).

3. 发明授权

US08273645B2 Method to attain low defectivity fully silicided gates 有权
标题翻译：获得低缺陷性全硅化物门的方法
公开(公告)号：US08273645B2
公开(公告)日：2012-09-25
申请号：US12537336
申请日：2009-08-07
申请人： Mark Robert Visokay , Freidoon Mehrad , Richard L. Guldi , Yaw Samuel Obeng
发明人： Mark Robert Visokay , Freidoon Mehrad , Richard L. Guldi , Yaw Samuel Obeng
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/66507 , H01L29/6659 , H01L29/7833
摘要： A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.
摘要翻译：公开了一种在MOS晶体管中形成完全硅化（FUSI）栅极的方法，其与源极/漏极硅化物形成中使用的湿蚀刻工艺兼容。栅极硅化物形成步骤产生富含金属的硅化物的顶层，其耐湿蚀刻工艺中的去除。有源区域上的阻挡层防止栅极硅化物形成期间的源/漏硅化物形成。去除阻挡层和源极/漏极金属带期间的湿蚀刻不能去除富金属栅极硅化物层。栅极硅化物的退火以产生具有所需化学计量的FUSI栅极被延迟直到形成源极/漏极硅化物。所公开的方法与镍和镍 - 铂硅化物工艺兼容。

4. 发明申请

US20100176462A1 METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE 审中-公开
标题翻译：同时硅化多晶硅栅极和半导体器件的源极/漏极的方法及相关器件
公开(公告)号：US20100176462A1
公开(公告)日：2010-07-15
申请号：US12731932
申请日：2010-03-25
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

5. 发明授权

US07727842B2 Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device 有权
标题翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法及相关器件
公开(公告)号：US07727842B2
公开(公告)日：2010-06-01
申请号：US11741519
申请日：2007-04-27
申请人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Steven A. Vitale , Joe G. Tran
IPC分类号： H01L21/8234
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
摘要翻译：同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及活跃区域。

6. 发明授权

US07396716B2 Method to obtain fully silicided poly gate 有权
标题翻译：获得完全硅化多孔的方法
公开(公告)号：US07396716B2
公开(公告)日：2008-07-08
申请号：US11201924
申请日：2005-08-11
申请人： Freidoon Mehrad , Shaofeng Yu , Joe G. Tran
发明人： Freidoon Mehrad , Shaofeng Yu , Joe G. Tran
IPC分类号： H01L21/311
CPC分类号： H01L21/823425 , H01L21/28097 , H01L21/31111 , H01L21/31116 , H01L21/823443 , H01L21/823468 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.
摘要翻译：本发明提供一种制造微电子器件的方法。在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。保护层710放置在覆盖层610和掺杂区域525之上，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。保护层710和覆盖层610的剩余部分保留在掺杂区域525之上。在栅极结构230的顶表面暴露的情况下，将金属结合到栅极结构中以形成栅电极230。

7. 发明申请

US20050208732A1 Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits 有权
公开(公告)号：US20050208732A1
公开(公告)日：2005-09-22
申请号：US11142483
申请日：2005-06-01
申请人： Zhihao Chen , Freidoon Mehrad , Brian Kirkpatrick , Jeff White , Edmund Russell , Jon Holt , Jason Mehigan
发明人： Zhihao Chen , Freidoon Mehrad , Brian Kirkpatrick , Jeff White , Edmund Russell , Jon Holt , Jason Mehigan
IPC分类号： H01L21/316 , H01L21/762 , H01L21/76 , H01L21/302 , H01L21/311 , H01L21/461
CPC分类号： H01L21/02126 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76235
摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

8. 发明申请

US20050101101A1 FORMING A TRENCH TO DEFINE ONE OR MORE ISOLATION REGIONS IN A SEMICONDUCTOR STRUCTURE 有权
标题翻译：形成一个半导体结构中定义一个或多个隔离区域的TRENCH
公开(公告)号：US20050101101A1
公开(公告)日：2005-05-12
申请号：US10703387
申请日：2003-11-06
申请人： Juanita DeLoach , Freidoon Mehrad , Brian Trentman , Troy Yocum
发明人： Juanita DeLoach , Freidoon Mehrad , Brian Trentman , Troy Yocum
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.
摘要翻译：在一个实施例中，在制造半导体器件中形成半导体结构的方法包括在衬底的表面上提供焊盘层，在焊盘层上提供氮化物层，并在氮化物层上提供牺牲氧化物层。在第一蚀刻步骤中，至少牺牲氧化物层和氮化物层被蚀刻以限定至少牺牲氧化物层和氮化物层的相对的基本垂直的表面。在第二蚀刻步骤中，蚀刻氮化物层，使得氮化物层的相对的基本上垂直的表面从牺牲氧化物层的相对的基本上垂直的表面凹陷，牺牲氧化物层基本上防止氮化物层的厚度减小蚀刻氮化物层的结果。在第三蚀刻步骤中，蚀刻衬底以形成延伸到衬底中的沟槽，用于限定与沟槽相邻的一个或多个隔离区域。

9. 发明授权

US06828213B2 Method to improve STI nano gap fill and moat nitride pull back 有权
标题翻译：改善STI纳米间隙填充和护环氮化物拉回的方法
公开(公告)号：US06828213B2
公开(公告)日：2004-12-07
申请号：US10376021
申请日：2003-02-28
申请人： Freidoon Mehrad , Zhihao Chen , Majid M. Mansoori
发明人： Freidoon Mehrad , Zhihao Chen , Majid M. Mansoori
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.
摘要翻译：通过生长衬垫氧化物，在衬垫氧化物上沉积氮化物层的步骤和护壁护理图案，护壁蚀刻和护城河清洁的步骤之后，提供了改善浅沟槽隔离（STI）间隙填充和齿隙氮化物拉回的方法，生长热氧化物的步骤，使一部分护环氮化物脱气; 沉积薄氮化物衬垫，蚀刻氮化物以在STI沟槽中形成薄的侧壁氮化物; 并在STI衬垫氧化和沉积氧化物以填充沟槽之前进行氧化物氢氟酸（HF）酸蒸气。

10. 发明授权

US06784056B2 Flash memory cell process using a hardmask 有权
标题翻译：闪存单元过程使用硬掩模
公开(公告)号：US06784056B2
公开(公告)日：2004-08-31
申请号：US10689947
申请日：2003-10-21
申请人： Paul A. Schneider , Freidoon Mehrad , John H. MacPeak
发明人： Paul A. Schneider , Freidoon Mehrad , John H. MacPeak
IPC分类号： H01L21336
CPC分类号： H01L21/28273 , H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielectric layer (45) during the hardmask (65) etch process.
摘要翻译：描述了使用硬掩模形成存储器结构的方法（65）。在SAS蚀刻工艺期间，硬掩模（65）保护第二多晶硅层（55）。此外，形成侧壁结构（95），其在硬掩模（65）蚀刻工艺期间保护多晶硅间介电层（45）。

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