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1. 发明授权

US08273645B2 Method to attain low defectivity fully silicided gates 有权
标题翻译：获得低缺陷性全硅化物门的方法
公开(公告)号：US08273645B2
公开(公告)日：2012-09-25
申请号：US12537336
申请日：2009-08-07
申请人： Mark Robert Visokay , Freidoon Mehrad , Richard L. Guldi , Yaw Samuel Obeng
发明人： Mark Robert Visokay , Freidoon Mehrad , Richard L. Guldi , Yaw Samuel Obeng
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/66507 , H01L29/6659 , H01L29/7833
摘要： A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.
摘要翻译：公开了一种在MOS晶体管中形成完全硅化（FUSI）栅极的方法，其与源极/漏极硅化物形成中使用的湿蚀刻工艺兼容。栅极硅化物形成步骤产生富含金属的硅化物的顶层，其耐湿蚀刻工艺中的去除。有源区域上的阻挡层防止栅极硅化物形成期间的源/漏硅化物形成。去除阻挡层和源极/漏极金属带期间的湿蚀刻不能去除富金属栅极硅化物层。栅极硅化物的退火以产生具有所需化学计量的FUSI栅极被延迟直到形成源极/漏极硅化物。所公开的方法与镍和镍 - 铂硅化物工艺兼容。

2. 发明申请

US20080176345A1 Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes 审中-公开
标题翻译：用于检测栅极电介质穿透的Ebeam检查和/或用于具有金属栅电极的晶体管的不完全硅化或金属化事件
公开(公告)号：US20080176345A1
公开(公告)日：2008-07-24
申请号：US11655483
申请日：2007-01-19
申请人： Shaofeng Yu , Richard L. Guldi , Jiong-Ping Lu , Freidoon Mehrad , Jae Hyun Park
发明人： Shaofeng Yu , Richard L. Guldi , Jiong-Ping Lu , Freidoon Mehrad , Jae Hyun Park
IPC分类号： H01L21/66
CPC分类号： H01L22/14
摘要： Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that subsequent resources are not unnecessarily expended. An electron beam or ebeam is directed at locations of a workpiece whereon on or more transistors are formed. Electrons that are resultantly emitted from these locations are detected and used to develop respective gray level values (GLV's). Gate dielectric punch through and/or incomplete silicidation or metallization events are identified by finding high or low GLV's relative to neighboring areas.
摘要翻译：识别在晶体管形成期间可能发生的栅极电介质穿透和/或不完全的硅化或金属化事件。在形成栅极电极之后才识别事件，以便表征用于过程控制目的的故障晶体管的程度，并且如果充分有缺陷，则废弃产品，使得后续资源不会被不必要地消耗。电子束或ebeam被引导到其上形成有多个晶体管的工件的位置。从这些位置发射的电子被检测并用于开发各自的灰度值（GLV's）。通过相对于相邻区域发现高或低GLV来鉴定栅极电介质穿透和/或不完全硅化或金属化事件。

3. 发明申请

US20090212793A1 STRUCTURES FOR TESTING AND LOCATING DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：用于集成电路测试和定位缺陷的结构
公开(公告)号：US20090212793A1
公开(公告)日：2009-08-27
申请号：US12037687
申请日：2008-02-26
申请人： Richard L. Guldi , Toan Tran , Deepak A. Ramappa
发明人： Richard L. Guldi , Toan Tran , Deepak A. Ramappa
IPC分类号： G01R31/305 , H01L23/58
CPC分类号： H01L22/14 , G01R31/2884 , G01R31/307 , H01L22/20 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.
摘要翻译：用于在半导体器件处理期间检测缺陷的方法可以包括提供具有电隔离应用的具有半导体层的衬底，并且在其上形成测试电路，将电子电流感应束引导到测试电路; 测量测试电路中的第一和第二接触焊盘之间的电流; 确定电子束感应电流（EBIC）; 以及基于EBIC和对应于EBIC的电子束的位置来识别测试电路中的一个或多个缺陷位置。测试电路可以包括并联连接的多个半导体器件，耦合到半导体器件的第一端子的第一接触焊盘以及耦合到与半导体器件相关联的衬底端子的至少第二接触焊盘。

4. 发明授权

US07228193B2 Methods for detecting structure dependent process defects 有权
公开(公告)号：US07228193B2
公开(公告)日：2007-06-05
申请号：US11204143
申请日：2005-08-15
申请人： Richard L. Guldi , Jae H. Park , Deepak A. Ramappa
发明人： Richard L. Guldi , Jae H. Park , Deepak A. Ramappa
IPC分类号： G06F19/00
CPC分类号： G03F7/7065
摘要： Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.

5. 发明授权

US07112540B2 Pretreatment for an electroplating process and an electroplating process in including the pretreatment 有权
标题翻译：包括预处理的电镀工艺和电镀工艺的预处理
公开(公告)号：US07112540B2
公开(公告)日：2006-09-26
申请号：US10766491
申请日：2004-01-28
申请人： Richard L. Guldi , Deepak Ramappa
发明人： Richard L. Guldi , Deepak Ramappa
IPC分类号： H01L21/31 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/76856 , H01L21/76873
摘要： The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other steps, placing a substrate 290 in an enclosure 200 being substantially devoid of unwanted contaminants and forming a material layer 310 over the substrate 290 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants. The electroplating process further includes forming a thin layer of oxide 410 over the material layer 310 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants during the forming the thin layer of oxide 410.
摘要翻译：本发明提供一种电镀工艺和一种用于制造集成电路的方法。除了其他步骤之外，电镀工艺还包括将衬底290放置在外壳200中，基本上没有不想要的污染物，并且在外壳200内的衬底290上形成材料层310，外壳200基本上没有不想要的污染物。电镀工艺还包括在外壳200内的材料层310上形成薄层的氧化物410，在形成薄层氧化物410期间，外壳200基本上没有不想要的污染物。

6. 发明授权

US07024950B2 Method for intelligent sampling of particulates in exhaust lines 有权
公开(公告)号：US07024950B2
公开(公告)日：2006-04-11
申请号：US09982656
申请日：2001-10-18
申请人： Richard L. Guldi , J. Michael Grobelny
发明人： Richard L. Guldi , J. Michael Grobelny
IPC分类号： G01N1/22 , G01N1/40 , G01N15/06 , G01N15/00 , H01L21/66
CPC分类号： H01L21/67253 , G01N1/2035 , G01N1/2202 , G01N15/0227 , G01N2001/2223 , G01N2015/0046 , G01N2015/0096 , G01N2015/0261
摘要： An in-situ particle monitor in an exhaust controls a particle sampler so that when a predetermined particle threshold is detected, the particle sampler is caused to gather samples from the exhaust in real-time. Electrical control signals are monitored to correlate variations in the signals with particle excursions for both analysis and sample collection triggering.

7. 发明授权

US06834117B1 X-ray defect detection in integrated circuit metallization 有权
标题翻译：集成电路金属化中的X射线缺陷检测
公开(公告)号：US06834117B1
公开(公告)日：2004-12-21
申请号：US09679796
申请日：2000-10-05
申请人： Satyavolu Papa Rao , Basab Chatterjee , Richard L. Guldi
发明人： Satyavolu Papa Rao , Basab Chatterjee , Richard L. Guldi
IPC分类号： G06K900
CPC分类号： G01N23/04 , H01L22/12
摘要： A system (25) for detecting defects in a semiconductor wafer (10), such defects including voids (V) present in metal conductors (2, 4) and plugs (7), is disclosed. An x-ray source (20) irradiates the wafer (10) through a first aperture array (24) having openings (26); a second aperture array (28) is located on the opposite side of the wafer (10) from the source (20), and has openings (30) that are aligned and registered with the openings (26) in the first aperture array (24). An array of x-ray detectors (31) is located adjacent to the second aperture array (28), with each detector (31) associated with one of the openings (30) of the second aperture array (28). The detectors (31) communicate signals regarding the magnitude of x-ray energy that is transmitted through wafer (10) at locations defined by the openings (26, 30) through aperture arrays (24, 28), to an analysis computer (34). A wafer translation system (32) indexes or otherwise moves the wafer (10) between the aperture arrays (24, 28). The analysis computer (34) generates an x-ray image of the wafer (10) from the detected x-ray energy, or alternatively compares the detected x-ray energy at locations of wafer (10) to automatically detect and distinguish defects.
摘要翻译：公开了一种用于检测半导体晶片（10）中的缺陷的系统（25），包括存在于金属导体（2,4）和插头（7）中的空隙（V）的缺陷。 X射线源（20）通过具有开口（26）的第一孔阵列（24）照射晶片（10）。第二孔径阵列（28）位于晶片（10）的与源极（20）相对的一侧上，并且具有与第一孔径阵列（24）中的开口（26）对准并对准的开口（30））。一组X射线检测器（31）位于第二孔径阵列（28）附近，每个检测器（31）与第二孔径阵列（28）的一个开口（30）相关联。检测器（31）将关于通过晶片（10）透射的x射线能量的大小的信号传送到通过孔阵列（24,28）由开口（26,30）限定的位置处的信号到分析计算机（34）。晶片平移系统（32）将晶片（10）指向或以其它方式移动在孔径阵列（24,28）之间。分析计算机（34）根据检测到的x射线能量产生晶片（10）的X射线图像，或者替代地比较晶片（10）的位置处的检测到的x射线能量，以自动检测和区分缺陷。

8. 发明授权

US06710364B2 Semiconductor wafer edge marking 有权
标题翻译：半导体晶圆边缘标记
公开(公告)号：US06710364B2
公开(公告)日：2004-03-23
申请号：US10178627
申请日：2002-06-20
申请人： Richard L. Guldi , Keith W. Melcher , John Williston
发明人： Richard L. Guldi , Keith W. Melcher , John Williston
IPC分类号： G01N2186
CPC分类号： H01L23/544 , B41M5/262 , H01L21/67282 , H01L2223/54413 , H01L2223/54433 , H01L2223/54493 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12t, 12b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed. The processing system (40) also includes a sensor (36) for sensing identification and orientation information from the wafer edge (E), and a process control computer (46) that receives signals corresponding to the identification information, for purposes of manufacturing data logging and process control.
摘要翻译：公开了沿着半导体晶片（20,20'）的边缘（E）的识别和取向信息的标记。信息可以通过沿着晶片（20,20'）的边缘（E）的平坦部分（14）或斜面（12t，12b）的一个或多个位置（10）处的激光标记来标记。晶片标记（10）可以例如通过2-D条形码进行编码。还公开了一种用于从载体（32）中的晶片（20,20'）读取识别信息的系统（30）。系统（30）包括用于从晶片边缘（E）感测来自晶片标记（10）的反射光并用于解码其识别和取向的传感器（36）。在来自传感器（36）的反馈（RFB）控制下的电动机（38）通过辊（39）旋转晶片（20,20'），直到晶片标记（10）由传感器（36）。还公开了一种包括可放置晶片（20,20'）的可旋转卡盘（41）的处理系统（40）。处理系统（40）还包括用于感测来自晶片边缘（E）的识别和取向信息的传感器（36），以及为了制造数据记录的目的而接收对应于识别信息的信号的过程控制计算机（46）和过程控制。

9. 发明授权

US06689686B2 System and method for electroplating fine geometries 有权
标题翻译：电镀精细几何的系统和方法
公开(公告)号：US06689686B2
公开(公告)日：2004-02-10
申请号：US10247000
申请日：2002-09-19
申请人： Richard L. Guldi , Wei-Yung Hsu
发明人： Richard L. Guldi , Wei-Yung Hsu
IPC分类号： H01L2144
CPC分类号： C25D17/001 , C25D5/04 , C25D5/18 , C25D7/123
摘要： An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is controlled by a controller. The rotation of the workpiece within a solution containing conductive material is controlled by a rotation controller. The current level and/or rotation of the workpiece is controlled in such a way that the non-uniform growth of large grains within the conductive film is minimized.
摘要翻译：描述了一种提供在工件上形成导电层的电镀系统。用于电镀工件的电流由控制器控制。在包含导电材料的溶液中的工件的旋转由旋转控制器控制。控制工件的当前水平和/或旋转，使得导电膜内大颗粒的不均匀生长最小化。

10. 发明授权

US06684125B2 In-situ randomization and recording of wafer processing order at process tools 有权
标题翻译：在工艺工具中原位随机化和记录晶圆处理顺序
公开(公告)号：US06684125B2
公开(公告)日：2004-01-27
申请号：US09997930
申请日：2001-11-30
申请人： Randolph W. Kahn , Kenneth G. Vickers , Richard L. Guldi , Edward J. Leonard , Yaojian Leng
发明人： Randolph W. Kahn , Kenneth G. Vickers , Richard L. Guldi , Edward J. Leonard , Yaojian Leng
IPC分类号： G06F700
CPC分类号： G05B19/41875 , G05B2219/32221 , G05B2219/32225 , G05B2219/45031 , H01L21/67276 , Y02P90/22 , Y10S414/137
摘要： Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.
摘要翻译：晶片顺序通过使用单独的晶片分级区域原位随机化，并且从该分段区域随机混洗晶片以洗牌晶片批次的处理顺序。在进程的发送和接收端都为每个晶片捕获位置数据。

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