专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080163813A1 ANNEAL OF EPITAXIAL LAYER IN A SEMICONDUCTOR DEVICE 有权
标题翻译：外延层在半导体器件中的退火
公开(公告)号：US20080163813A1
公开(公告)日：2008-07-10
申请号：US11620987
申请日：2007-01-08
申请人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
发明人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
IPC分类号： H01L21/02 , C30B19/12
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/665 , H01L29/66636 , H01L29/7834
摘要： An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
摘要翻译：包含IV族元素组合的外延生长的晶体半导体层的退火。该层含有碳和锡中的至少一种。外延生长材料层在峰值温度的10％以内，在1000〜1400摄氏度的温度下退火不超过100毫秒。退火例如通过激光退火或闪光灯退火来进行。有限时间退火可以改善晶体管的载流子迁移率。

2. 发明授权

US07416605B2 Anneal of epitaxial layer in a semiconductor device 有权
标题翻译：在半导体器件中退火外延层
公开(公告)号：US07416605B2
公开(公告)日：2008-08-26
申请号：US11620987
申请日：2007-01-08
申请人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
发明人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
IPC分类号： C30B25/14 , C30B25/12
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/665 , H01L29/66636 , H01L29/7834
摘要： An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
摘要翻译：包含IV族元素组合的外延生长的晶体半导体层的退火。该层含有碳和锡中的至少一种。外延生长材料层在峰值温度的10％以内，在1000〜1400摄氏度的温度下退火不超过100毫秒。退火例如通过激光退火或闪光灯退火来进行。有限时间退火可以改善晶体管的载流子迁移率。

3. 发明申请

US20080293192A1 SEMICONDUCTOR DEVICE WITH STRESSORS AND METHODS THEREOF 审中-公开
标题翻译：具有抗压件的半导体器件及其方法
公开(公告)号：US20080293192A1
公开(公告)日：2008-11-27
申请号：US11751724
申请日：2007-05-22
申请人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski
发明人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/26506 , H01L29/665 , H01L29/66628 , H01L29/66772 , H01L29/7843
摘要： A semiconductor device is formed in a semiconductor layer. A gate dielectric is formed over a top surface of the semiconductor layer. A gate stack is over the gate dielectric. A sidewall spacer is formed around the gate stack. Using the sidewall spacer as a mask, an implant is performed to form deep source/drain regions in the semiconductor layer. Silicon carbon regions are formed on the deep source/drain regions and a top surface of the gate stack. The silicon carbon regions are silicided with nickel.
摘要翻译：在半导体层中形成半导体器件。在半导体层的顶表面上形成栅极电介质。栅极堆叠在栅极电介质上方。在栅堆叠周围形成侧壁间隔物。使用侧壁间隔件作为掩模，进行注入以在半导体层中形成深的源极/漏极区域。在深源极/漏极区域和栅极堆叠的顶表面上形成硅碳区域。硅碳区域用镍硅化。

4. 发明申请

US20080299724A1 METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR 失效
标题翻译：制造具有嵌入式压力器的半导体器件的方法
公开(公告)号：US20080299724A1
公开(公告)日：2008-12-04
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。

5. 发明授权

US07736957B2 Method of making a semiconductor device with embedded stressor 失效
标题翻译：制造具有嵌入式应力源的半导体器件的方法
公开(公告)号：US07736957B2
公开(公告)日：2010-06-15
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。

6. 发明授权

US07687354B2 Fabrication of a semiconductor device with stressor 失效
标题翻译：用应力源制造半导体器件
公开(公告)号：US07687354B2
公开(公告)日：2010-03-30
申请号：US12040394
申请日：2008-02-29
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Stefan Zollner
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/165 , H01L29/66553 , H01L29/66583 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
摘要翻译：在半导体制造工艺中，在衬底上形成外延层，其中在外延层和衬底之间存在晶格失配。形成具有开口的硬掩模覆盖在外延层上。通过外延层形成凹槽并进入衬底。凹槽基本上对准硬掩模中的开口。半导体器件的沟道区形成在凹部中。

7. 发明申请

US20090221119A1 FABRICATION OF A SEMICONDUCTOR DEVICE WITH STRESSOR 失效
标题翻译：具有应力的半导体器件的制造
公开(公告)号：US20090221119A1
公开(公告)日：2009-09-03
申请号：US12040394
申请日：2008-02-29
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Stefan Zollner
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/165 , H01L29/66553 , H01L29/66583 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
摘要翻译：在半导体制造工艺中，在衬底上形成外延层，其中在外延层和衬底之间存在晶格失配。形成具有开口的硬掩模覆盖在外延层上。通过外延层形成凹槽并进入衬底。凹槽基本上对准硬掩模中的开口。半导体器件的沟道区形成在凹部中。

8. 发明授权

US07820530B2 Efficient body contact field effect transistor with reduced body resistance 有权
标题翻译：高效的身体接触场效应晶体管具有降低的体电阻
公开(公告)号：US07820530B2
公开(公告)日：2010-10-26
申请号：US12243639
申请日：2008-10-01
申请人： Byoung W. Min , Stefan Zollner , Qingqing Liang
发明人： Byoung W. Min , Stefan Zollner , Qingqing Liang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/41758 , H01L21/26506 , H01L21/26586 , H01L29/4238 , H01L29/4983 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.
摘要翻译：一种形成接触体的SOI晶体管的方法包括形成具有体接触区域（120），体接近区域（121）和有源区域（122）的半导体层（103）。通过蚀刻金属栅极结构（107,108）在有源区中形成SOI晶体管，以形成在有源区上形成的第一部分（130），以及形成在身体通路的至少一部分上的第二部分（131）地区。通过以非垂直角将离子（203,301）注入到身体存取区域中的注入区域（204,302）中，以便侵入蚀刻金属栅极结构的有源区域和/或第二部分下方，随后可以在身体接触区域和植入区域上形成硅化物（306），从而减少身体接近区域中的耗尽区域（308）的形成。

9. 发明申请

US20100081239A1 Efficient Body Contact Field Effect Transistor with Reduced Body Resistance 有权
标题翻译：高效的体接触场效应晶体管，具有降低体电阻
公开(公告)号：US20100081239A1
公开(公告)日：2010-04-01
申请号：US12243639
申请日：2008-10-01
申请人： Byoung W. Min , Stefan Zollner , Qingqing Liang
发明人： Byoung W. Min , Stefan Zollner , Qingqing Liang
IPC分类号： H01L21/331
CPC分类号： H01L29/41758 , H01L21/26506 , H01L21/26586 , H01L29/4238 , H01L29/4983 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.
摘要翻译：一种形成接触体的SOI晶体管的方法包括形成具有体接触区域（120），体接近区域（121）和有源区域（122）的半导体层（103）。通过蚀刻金属栅极结构（107,108）在有源区中形成SOI晶体管，以形成在有源区上形成的第一部分（130），以及形成在身体通路的至少一部分上的第二部分（131）地区。通过以非垂直角将离子（203,301）注入到身体存取区域中的注入区域（204,302）中，以便侵入蚀刻金属栅极结构的有源区域和/或第二部分下方，随后可以在身体接触区域和植入区域上形成硅化物（306），从而减少身体接近区域中的耗尽区域（308）的形成。

10. 发明授权

US07560354B2 Process of forming an electronic device including a doped semiconductor layer 有权
标题翻译：形成包括掺杂半导体层的电子器件的工艺
公开(公告)号：US07560354B2
公开(公告)日：2009-07-14
申请号：US11835643
申请日：2007-08-08
申请人： Stefan Zollner , Bich-Yen Nguyen
发明人： Stefan Zollner , Bich-Yen Nguyen
IPC分类号： H01L21/336
CPC分类号： H01L21/28035 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/2807 , H01L29/4916 , H01L29/66636 , H01L29/7833
摘要： A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
摘要翻译：工艺可以包括在衬底上形成掺杂半导体层。该方法还可以包括执行减少沿着包括衬底和掺杂半导体层的工件的暴露表面的掺杂剂含量的动作。在形成掺杂半导体层之后并且在掺杂半导体层暴露于室内环境之前执行该动作。在特定实施例中，掺杂半导体层包括半导体材料，其包括选自由C，Si和Ge组成的组中的至少两种元素的组合，并且掺杂半导体层还包括掺杂剂，例如磷，砷，硼等。该作用可以包括形成封装层，将掺杂半导体层暴露于辐射，退火掺杂半导体层，或其任何组合。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式