专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080299724A1 METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR 失效
标题翻译：制造具有嵌入式压力器的半导体器件的方法
公开(公告)号：US20080299724A1
公开(公告)日：2008-12-04
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。

2. 发明授权

US07736957B2 Method of making a semiconductor device with embedded stressor 失效
标题翻译：制造具有嵌入式应力源的半导体器件的方法
公开(公告)号：US07736957B2
公开(公告)日：2010-06-15
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。

3. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

4. 发明授权

US07781277B2 Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit 有权
标题翻译：应变绝缘子集成电路中布局优化的选择性单轴应力松弛
公开(公告)号：US07781277B2
公开(公告)日：2010-08-24
申请号：US11383113
申请日：2006-05-12
申请人： Bich-Yen Nguyen , Voon-Yew Thean
发明人： Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/0207 , H01L29/1033 , H01L29/41758 , H01L29/41775 , H01L29/6659 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.
摘要翻译：集成电路包括NMOS和PMOS晶体管。 NMOS具有分别具有沿着第一和第二轴的第一和第二应力值的应变通道。 PMOS具有沿第一和第二轴具有第三和第四应力值的应变通道。第一值应力与第三值不同，第二值与第四值不同。 NMOS和PMOS具有公共长度（L）和有效宽度（W），但扩散长度（SA）和/或源极/漏极（WS）的宽度不同。 NMOS WS可能超过PMOS WS。 NMOS可以包括位于栅极下方的有源层中的多个电介质结构。 PMOS的SA可以小于NMOS的SA。集成电路可以包括氮化硅在NMOS上的拉伸应力源和在PMOS上的氮化硅的压应力。

5. 发明授权

US07737018B2 Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer 有权
标题翻译：形成包括形成栅电极层并形成图案化掩模层的电子器件的工艺
公开(公告)号：US07737018B2
公开(公告)日：2010-06-15
申请号：US11671748
申请日：2007-02-06
申请人： Leo Mathew , Voon-Yew Thean , Vishal P. Trivedi
发明人： Leo Mathew , Voon-Yew Thean , Vishal P. Trivedi
IPC分类号： H01L21/3205
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/32139 , H01L29/4966
摘要： A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.
摘要翻译：形成电子器件的工艺可以包括形成栅极电极层并形成图案化掩模层。在第一方面，在去除栅极电极层的基本上所有下部之前进行处理操作。在第二方面，在形成栅极电极层之前形成栅极电介质层，并且在去除图案化掩模层之后并且在形成另一个掩模层之前，一部分栅极电介质层被曝光。在其中将部分或全部部分将被去除或消耗的过程中，栅电极层的一部分保持覆盖。通过使用这种处理形成电子器件，可以显着地减少执行后续处理时对栅电极结构的损坏。

6. 发明申请

US20090286387A1 Modulation of Tantalum-Based Electrode Workfunction 审中-公开
标题翻译：钽电极工作功能的调制
公开(公告)号：US20090286387A1
公开(公告)日：2009-11-19
申请号：US12122178
申请日：2008-05-16
申请人： David C. Gilmer , Srikanth B. Samavedam , James K. Schaeffer , Voon-Yew Thean
发明人： David C. Gilmer , Srikanth B. Samavedam , James K. Schaeffer , Voon-Yew Thean
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4975
摘要： A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.
摘要翻译：一种半导体工艺和装置，通过在栅介质层（12）上形成第一导电层（14）制造金属栅电极，然后选择性地将氮引入PMOS器件区域（1）中的第一导电层（14）的部分），通过在形成于PMOS器件区域（1）中的含氮扩散层（22）退火（42），或者在NMOS器件区域（2）被掩蔽的同时执行氨退火工艺（82）。通过将氮引入到第一导电层（14）中，功函数被调制到PMOS带边缘。

7. 发明申请

US20070235807A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US20070235807A1
公开(公告)日：2007-10-11
申请号：US11742955
申请日：2007-05-01
申请人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
发明人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

8. 发明申请

US20070218707A1 Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same 有权
标题翻译：包括在绝缘层上具有不同厚度的半导体岛的电子器件及其形成方法
公开(公告)号：US20070218707A1
公开(公告)日：2007-09-20
申请号：US11375893
申请日：2006-03-15
申请人： Mariam Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/31
CPC分类号： H01L21/32 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/84
摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.
摘要翻译：形成电子器件的方法可以包括在覆盖在衬底上的半导体层上形成图案化的抗氧化层，并且图案化半导体层以形成半导体岛。半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。该方法还可以包括沿着半导体岛的一侧形成耐氧化材料或者沿半导体岛的一侧选择性地沉积半导体材料。该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛，并将抗氧化材料转化为含氧环境。

9. 发明申请

US20070205421A1 SEMICONDUCTOR OPTICAL DEVICES AND METHOD FOR FORMING 失效
公开(公告)号：US20070205421A1
公开(公告)日：2007-09-06
申请号：US11465395
申请日：2006-08-17
申请人： Leo Mathew , Yang Du , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Voon-Yew Thean
IPC分类号： H01L33/00 , H01L31/12 , H01L27/15 , H01L29/26
CPC分类号： H01S5/0262 , B82Y20/00 , H01L27/14643 , H01L27/14687 , H01L29/66803 , H01L29/785 , H01L31/0384 , H01L31/105 , H01L33/08 , H01L33/18 , H01L33/24 , H01S3/169 , H01S5/0261 , H01S5/0421 , H01S5/0425 , H01S5/2205 , H01S5/304 , Y10S977/95
摘要： A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together. The optical devices may also be integrated with other types of semiconductor devices, such as vertical field-effect transistors.

10. 发明授权

US07265004B2 Electronic devices including a semiconductor layer and a process for forming the same 有权
标题翻译：包括半导体层的电子器件及其形成方法
公开(公告)号：US07265004B2
公开(公告)日：2007-09-04
申请号：US11273092
申请日：2005-11-14
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式