专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07560354B2 Process of forming an electronic device including a doped semiconductor layer 有权
标题翻译：形成包括掺杂半导体层的电子器件的工艺
公开(公告)号：US07560354B2
公开(公告)日：2009-07-14
申请号：US11835643
申请日：2007-08-08
申请人： Stefan Zollner , Bich-Yen Nguyen
发明人： Stefan Zollner , Bich-Yen Nguyen
IPC分类号： H01L21/336
CPC分类号： H01L21/28035 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/2807 , H01L29/4916 , H01L29/66636 , H01L29/7833
摘要： A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
摘要翻译：工艺可以包括在衬底上形成掺杂半导体层。该方法还可以包括执行减少沿着包括衬底和掺杂半导体层的工件的暴露表面的掺杂剂含量的动作。在形成掺杂半导体层之后并且在掺杂半导体层暴露于室内环境之前执行该动作。在特定实施例中，掺杂半导体层包括半导体材料，其包括选自由C，Si和Ge组成的组中的至少两种元素的组合，并且掺杂半导体层还包括掺杂剂，例如磷，砷，硼等。该作用可以包括形成封装层，将掺杂半导体层暴露于辐射，退火掺杂半导体层，或其任何组合。

2. 发明申请

US20090042373A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A DOPED SEMICONDUCTOR LAYER 有权
标题翻译：形成包含掺杂半导体层的电子器件的工艺
公开(公告)号：US20090042373A1
公开(公告)日：2009-02-12
申请号：US11835643
申请日：2007-08-08
申请人： Stefan Zollner , Bich-Yen Nguyen
发明人： Stefan Zollner , Bich-Yen Nguyen
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L21/28035 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/2807 , H01L29/4916 , H01L29/66636 , H01L29/7833
摘要： A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
摘要翻译：工艺可以包括在衬底上形成掺杂半导体层。该方法还可以包括执行减少沿着包括衬底和掺杂半导体层的工件的暴露表面的掺杂剂含量的动作。在形成掺杂半导体层之后并且在掺杂半导体层暴露于室内环境之前执行该动作。在特定实施例中，掺杂半导体层包括半导体材料，其包括选自由C，Si和Ge组成的组中的至少两种元素的组合，并且掺杂半导体层还包括掺杂剂，例如磷，砷，硼等。该作用可以包括形成封装层，将掺杂半导体层暴露于辐射，退火掺杂半导体层，或其任何组合。

3. 发明授权

US08842945B2 Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates 有权
标题翻译：形成三维集成半导体系统的方法，包括光敏元件和绝缘体上半导体衬底
公开(公告)号：US08842945B2
公开(公告)日：2014-09-23
申请号：US13206299
申请日：2011-08-09
申请人： Bich-Yen Nguyen , Mariam Sadaka
发明人： Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： G02B6/12 , H01L25/16 , H01L27/06 , H01L31/103
CPC分类号： H01L25/167 , G02B6/12002 , G02B6/12004 , H01L27/0688 , H01L27/1203 , H01L31/103 , H01L33/34 , H01L2924/0002 , H01L2924/00
摘要： Three dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.
摘要翻译：三维集成的半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。光学互连可操作地耦合到光活性器件。半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。

4. 发明授权

US08654602B2 Pseudo-inverter circuit on SeOI 有权
标题翻译： SeOI上的伪逆变电路
公开(公告)号：US08654602B2
公开(公告)日：2014-02-18
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

5. 发明申请

US20110242926A1 PSEUDO-INVERTER CIRCUIT ON SeO1 有权
标题翻译： PSO1上的PSEUDO-INVERTER电路
公开(公告)号：US20110242926A1
公开(公告)日：2011-10-06
申请号：US12793553
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F1/10
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

6. 发明授权

US07943988B2 Power MOSFET with a gate structure of different material 有权
标题翻译：功率MOSFET具有栅极结构不同的材料
公开(公告)号：US07943988B2
公开(公告)日：2011-05-17
申请号：US12205438
申请日：2008-09-05
申请人： Daniel Pham , Bich-Yen Nguyen
发明人： Daniel Pham , Bich-Yen Nguyen
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28105 , H01L29/42372
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.
摘要翻译：半导体器件包括第一导电类型和第一掺杂浓度的半导体层。用作第一导电类型的漏极的第一半导体区域具有比半导体层更低的掺杂浓度，并且在半导体层之上。栅极电介质在第一半导体区域之上。栅极电介质上的栅极电极在中心部分的相对侧上具有含金属的中心部分和第一和第二硅部分。用作第二导电类型的沟道的第二半导体区域具有在第一硅部分下面的第一部分和栅极电介质。用作第一导电类型的源的第三半导体区域与第二半导体区域的第一部分横向相邻。置换硅的含金属中心部分将源极增加到漏极击穿电压。

7. 发明授权

US07821067B2 Electronic devices including a semiconductor layer 有权
标题翻译：包括半导体层的电子器件
公开(公告)号：US07821067B2
公开(公告)日：2010-10-26
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

8. 发明授权

US07800141B2 Electronic device including a semiconductor fin 有权
标题翻译：包括半导体鳍片的电子设备
公开(公告)号：US07800141B2
公开(公告)日：2010-09-21
申请号：US12174357
申请日：2008-07-16
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

9. 发明授权

US07781839B2 Structure and method for strained transistor directly on insulator 有权
标题翻译：应变晶体管直接在绝缘体上的结构和方法
公开(公告)号：US07781839B2
公开(公告)日：2010-08-24
申请号：US11694273
申请日：2007-03-30
申请人： Voon-Yew Thean , Bich-Yen Nguyen
发明人： Voon-Yew Thean , Bich-Yen Nguyen
IPC分类号： H01L27/092
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7842
摘要： A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.
摘要翻译：提供一种半导体器件（10），其包括衬底（12）和形成在衬底上的氧化物层（14）。半导体器件还包括具有直接形成在氧化物层上的第一晶格常数的第一半导体层（16）。半导体器件还包括具有直接形成在第一半导体层上的第二晶格常数的第二半导体层（26），其中第二晶格常数不同于第一晶格常数。

10. 发明授权

US07700420B2 Integrated circuit with different channel materials for P and N channel transistors and method therefor 有权
标题翻译：用于P和N沟道晶体管的不同沟道材料的集成电路及其方法
公开(公告)号：US07700420B2
公开(公告)日：2010-04-20
申请号：US11402395
申请日：2006-04-12
申请人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White
发明人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8258 , H01L27/1203
摘要： A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.
摘要翻译：衬底包括第一区域和第二区域。第一区域包括III族氮化物层，第二区域包括第一半导体层。在III族氮化物层上形成第一晶体管（例如n型晶体管），并且在第一半导体层上形成第二晶体管（例如p型晶体管）。 III族氮化物层可以是氮化铟。在第一区域中，衬底可以包括第二半导体层，在第二半导体层上的渐变过渡层，以及过渡层上的缓冲层，其中III族氮化物层在缓冲层之上。在第二区域中，衬底可以包括第二半导体层和在第二半导体层上的绝缘层，其中第一半导体层在绝缘层之上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式