专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110012629A1 REPLACEMENT-GATE-COMPATIBLE PROGRAMMABLE ELECTRICAL ANTIFUSE 有权
标题翻译：替代可控可编程电抗器
公开(公告)号：US20110012629A1
公开(公告)日：2011-01-20
申请号：US12503116
申请日：2009-07-15
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L27/06 , H01L21/28 , H01H37/76
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

2. 发明授权

US07709303B2 Process for forming an electronic device including a fin-type structure 有权
标题翻译：用于形成包括翅片型结构的电子设备的方法
公开(公告)号：US07709303B2
公开(公告)日：2010-05-04
申请号：US11328668
申请日：2006-01-10
申请人： James D. Burnett , Leo Mathew , Byoung W. Min
发明人： James D. Burnett , Leo Mathew , Byoung W. Min
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.
摘要翻译：用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

3. 发明申请

US20100078727A1 eFuse and Resistor Structures and Method for Forming Same in Active Region 审中-公开
标题翻译： eFuse和电阻结构及其在活跃区域中形成的方法
公开(公告)号：US20100078727A1
公开(公告)日：2010-04-01
申请号：US12243313
申请日：2008-10-01
申请人： Byoung W. Min , Satya N. Chakravarti
发明人： Byoung W. Min , Satya N. Chakravarti
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/44
CPC分类号： H01L21/84 , H01L23/5228 , H01L23/5256 , H01L27/0629 , H01L27/1203 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fabrication process and apparatus are provided for forming passive devices, such as a fuse (93) or resistor (95), in an active substrate region (103) by using heavy ion implantation (30) and annealing (40) to selectively form polycrystalline structures (42, 44) from a monocrystalline active layer (103), while retaining the single crystalline regions in the active layer (103) for use in forming active devices, such as NMOS and/or PMOS transistors (94). As disclosed, fuse structures (93) may be fabricated by forming silicide (90) in an upper region of the polycrystalline structure (42), while resistor structures (95) may be simultaneously formed from polycrystalline structure (44) which is selectively masked during silicide formation.
摘要翻译：提供半导体制造工艺和装置，用于通过使用重离子注入（30）和退火（40）在有源衬底区域（103）中形成无源器件，例如熔丝（93）或电阻器（95），以选择性地形成同时保持有源层（103）中的单晶区域用于形成诸如NMOS和/或PMOS晶体管（94）的有源器件的单晶有源层（103）的多晶结构（42,44）。如所公开的那样，可以通过在多晶结构（42）的上部区域中形成硅化物（90）来制造熔丝结构（93），而电阻器结构（95）可以由多晶结构（44）同时形成，多晶结构（44）在硅化物形成。

4. 发明授权

US06921961B2 Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region 有权
标题翻译：具有从相对侧电接触的半导体器件，包括形成在扩散区域的底表面处的端部的通孔
公开(公告)号：US06921961B2
公开(公告)日：2005-07-26
申请号：US10946758
申请日：2004-09-22
申请人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
发明人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L29/00 , H01L29/06 , H01L29/40
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连件（68）连接的直接下伏的无源器件（例如电容器）（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

5. 发明授权

US09082650B2 Integrated split gate non-volatile memory cell and logic structure 有权
标题翻译：集成分离门非易失性存储单元和逻辑结构
公开(公告)号：US09082650B2
公开(公告)日：2015-07-14
申请号：US13971987
申请日：2013-08-21
申请人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Byoung W. Min , Jane A. Yater
发明人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Byoung W. Min , Jane A. Yater
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L21/28 , H01L29/423
CPC分类号： H01L27/11517 , H01L21/28273 , H01L27/11534 , H01L29/42332 , H01L29/66545 , H01L29/66825
摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.
摘要翻译：制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。间隔选择栅极通过沉积保形层，随后进行回蚀而形成。图案化蚀刻导致将电荷存储层的一部分留在选择栅上。形成在逻辑区域中的虚拟栅极结构具有由绝缘层包围的虚拟栅极。执行化学抛光导致电荷存储层的顶表面与虚拟栅极结构的顶表面共面。用包括另外的化学机械抛光的金属逻辑门来替代虚拟栅极结构的一部分导致电荷存储层的顶表面与金属逻辑门共面。

6. 发明授权

US09059006B2 Replacement-gate-compatible programmable electrical antifuse 有权
标题翻译：替换门兼容可编程电气反熔丝
公开(公告)号：US09059006B2
公开(公告)日：2015-06-16
申请号：US13523120
申请日：2012-06-14
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L23/52 , H01L29/10 , H01L27/06 , H01L23/525 , H01L27/112 , H01L29/66 , H01L29/49 , H01L29/78
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触点中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

7. 发明授权

US08237457B2 Replacement-gate-compatible programmable electrical antifuse 有权
标题翻译：替换门兼容可编程电气反熔丝
公开(公告)号：US08237457B2
公开(公告)日：2012-08-07
申请号：US12503116
申请日：2009-07-15
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L23/52 , H01L29/10
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

8. 发明授权

US07820530B2 Efficient body contact field effect transistor with reduced body resistance 有权
标题翻译：高效的身体接触场效应晶体管具有降低的体电阻
公开(公告)号：US07820530B2
公开(公告)日：2010-10-26
申请号：US12243639
申请日：2008-10-01
申请人： Byoung W. Min , Stefan Zollner , Qingqing Liang
发明人： Byoung W. Min , Stefan Zollner , Qingqing Liang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/41758 , H01L21/26506 , H01L21/26586 , H01L29/4238 , H01L29/4983 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.
摘要翻译：一种形成接触体的SOI晶体管的方法包括形成具有体接触区域（120），体接近区域（121）和有源区域（122）的半导体层（103）。通过蚀刻金属栅极结构（107,108）在有源区中形成SOI晶体管，以形成在有源区上形成的第一部分（130），以及形成在身体通路的至少一部分上的第二部分（131）地区。通过以非垂直角将离子（203,301）注入到身体存取区域中的注入区域（204,302）中，以便侵入蚀刻金属栅极结构的有源区域和/或第二部分下方，随后可以在身体接触区域和植入区域上形成硅化物（306），从而减少身体接近区域中的耗尽区域（308）的形成。

9. 发明授权

US07754560B2 Integrated circuit using FinFETs and having a static random access memory (SRAM) 有权
标题翻译：使用FinFET并具有静态随机存取存储器（SRAM）的集成电路
公开(公告)号：US07754560B2
公开(公告)日：2010-07-13
申请号：US11328779
申请日：2006-01-10
申请人： James D. Burnett , Leo Mathew , Byoung W. Min
发明人： James D. Burnett , Leo Mathew , Byoung W. Min
IPC分类号： H01L21/8244 , H01L29/78
CPC分类号： H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).
摘要翻译：集成电路包括逻辑电路和存储单元。逻辑电路包括P沟道晶体管，并且存储单元包括P沟道晶体管。逻辑电路的P沟道晶体管包括沟道区。沟道区具有位于具有（110）表面取向的半导体结构的侧壁的部分。位于沿着侧壁的通道区域的部分具有第一垂直尺寸，其大于沿着具有表面的半导体结构的侧壁的存储单元的P沟道晶体管的沟道区的任何部分的垂直尺寸（110）的方向。

10. 发明申请

US20100081239A1 Efficient Body Contact Field Effect Transistor with Reduced Body Resistance 有权
标题翻译：高效的体接触场效应晶体管，具有降低体电阻
公开(公告)号：US20100081239A1
公开(公告)日：2010-04-01
申请号：US12243639
申请日：2008-10-01
申请人： Byoung W. Min , Stefan Zollner , Qingqing Liang
发明人： Byoung W. Min , Stefan Zollner , Qingqing Liang
IPC分类号： H01L21/331
CPC分类号： H01L29/41758 , H01L21/26506 , H01L21/26586 , H01L29/4238 , H01L29/4983 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.
摘要翻译：一种形成接触体的SOI晶体管的方法包括形成具有体接触区域（120），体接近区域（121）和有源区域（122）的半导体层（103）。通过蚀刻金属栅极结构（107,108）在有源区中形成SOI晶体管，以形成在有源区上形成的第一部分（130），以及形成在身体通路的至少一部分上的第二部分（131）地区。通过以非垂直角将离子（203,301）注入到身体存取区域中的注入区域（204,302）中，以便侵入蚀刻金属栅极结构的有源区域和/或第二部分下方，随后可以在身体接触区域和植入区域上形成硅化物（306），从而减少身体接近区域中的耗尽区域（308）的形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式