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1. 发明授权

US07820530B2 Efficient body contact field effect transistor with reduced body resistance 有权
标题翻译：高效的身体接触场效应晶体管具有降低的体电阻
公开(公告)号：US07820530B2
公开(公告)日：2010-10-26
申请号：US12243639
申请日：2008-10-01
申请人： Byoung W. Min , Stefan Zollner , Qingqing Liang
发明人： Byoung W. Min , Stefan Zollner , Qingqing Liang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/41758 , H01L21/26506 , H01L21/26586 , H01L29/4238 , H01L29/4983 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.
摘要翻译：一种形成接触体的SOI晶体管的方法包括形成具有体接触区域（120），体接近区域（121）和有源区域（122）的半导体层（103）。通过蚀刻金属栅极结构（107,108）在有源区中形成SOI晶体管，以形成在有源区上形成的第一部分（130），以及形成在身体通路的至少一部分上的第二部分（131）地区。通过以非垂直角将离子（203,301）注入到身体存取区域中的注入区域（204,302）中，以便侵入蚀刻金属栅极结构的有源区域和/或第二部分下方，随后可以在身体接触区域和植入区域上形成硅化物（306），从而减少身体接近区域中的耗尽区域（308）的形成。

2. 发明申请

US20100081239A1 Efficient Body Contact Field Effect Transistor with Reduced Body Resistance 有权
标题翻译：高效的体接触场效应晶体管，具有降低体电阻
公开(公告)号：US20100081239A1
公开(公告)日：2010-04-01
申请号：US12243639
申请日：2008-10-01
申请人： Byoung W. Min , Stefan Zollner , Qingqing Liang
发明人： Byoung W. Min , Stefan Zollner , Qingqing Liang
IPC分类号： H01L21/331
CPC分类号： H01L29/41758 , H01L21/26506 , H01L21/26586 , H01L29/4238 , H01L29/4983 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.
摘要翻译：一种形成接触体的SOI晶体管的方法包括形成具有体接触区域（120），体接近区域（121）和有源区域（122）的半导体层（103）。通过蚀刻金属栅极结构（107,108）在有源区中形成SOI晶体管，以形成在有源区上形成的第一部分（130），以及形成在身体通路的至少一部分上的第二部分（131）地区。通过以非垂直角将离子（203,301）注入到身体存取区域中的注入区域（204,302）中，以便侵入蚀刻金属栅极结构的有源区域和/或第二部分下方，随后可以在身体接触区域和植入区域上形成硅化物（306），从而减少身体接近区域中的耗尽区域（308）的形成。

3. 发明申请

US20110012629A1 REPLACEMENT-GATE-COMPATIBLE PROGRAMMABLE ELECTRICAL ANTIFUSE 有权
标题翻译：替代可控可编程电抗器
公开(公告)号：US20110012629A1
公开(公告)日：2011-01-20
申请号：US12503116
申请日：2009-07-15
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L27/06 , H01L21/28 , H01H37/76
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

4. 发明授权

US07709303B2 Process for forming an electronic device including a fin-type structure 有权
标题翻译：用于形成包括翅片型结构的电子设备的方法
公开(公告)号：US07709303B2
公开(公告)日：2010-05-04
申请号：US11328668
申请日：2006-01-10
申请人： James D. Burnett , Leo Mathew , Byoung W. Min
发明人： James D. Burnett , Leo Mathew , Byoung W. Min
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.
摘要翻译：用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

5. 发明申请

US20100078727A1 eFuse and Resistor Structures and Method for Forming Same in Active Region 审中-公开
标题翻译： eFuse和电阻结构及其在活跃区域中形成的方法
公开(公告)号：US20100078727A1
公开(公告)日：2010-04-01
申请号：US12243313
申请日：2008-10-01
申请人： Byoung W. Min , Satya N. Chakravarti
发明人： Byoung W. Min , Satya N. Chakravarti
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/44
CPC分类号： H01L21/84 , H01L23/5228 , H01L23/5256 , H01L27/0629 , H01L27/1203 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fabrication process and apparatus are provided for forming passive devices, such as a fuse (93) or resistor (95), in an active substrate region (103) by using heavy ion implantation (30) and annealing (40) to selectively form polycrystalline structures (42, 44) from a monocrystalline active layer (103), while retaining the single crystalline regions in the active layer (103) for use in forming active devices, such as NMOS and/or PMOS transistors (94). As disclosed, fuse structures (93) may be fabricated by forming silicide (90) in an upper region of the polycrystalline structure (42), while resistor structures (95) may be simultaneously formed from polycrystalline structure (44) which is selectively masked during silicide formation.
摘要翻译：提供半导体制造工艺和装置，用于通过使用重离子注入（30）和退火（40）在有源衬底区域（103）中形成无源器件，例如熔丝（93）或电阻器（95），以选择性地形成同时保持有源层（103）中的单晶区域用于形成诸如NMOS和/或PMOS晶体管（94）的有源器件的单晶有源层（103）的多晶结构（42,44）。如所公开的那样，可以通过在多晶结构（42）的上部区域中形成硅化物（90）来制造熔丝结构（93），而电阻器结构（95）可以由多晶结构（44）同时形成，多晶结构（44）在硅化物形成。

6. 发明授权

US06921961B2 Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region 有权
标题翻译：具有从相对侧电接触的半导体器件，包括形成在扩散区域的底表面处的端部的通孔
公开(公告)号：US06921961B2
公开(公告)日：2005-07-26
申请号：US10946758
申请日：2004-09-22
申请人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
发明人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L29/00 , H01L29/06 , H01L29/40
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连件（68）连接的直接下伏的无源器件（例如电容器）（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

7. 发明授权

US07927934B2 SOI semiconductor device with body contact and method thereof 有权
标题翻译：具有身体接触的SOI半导体器件及其方法
公开(公告)号：US07927934B2
公开(公告)日：2011-04-19
申请号：US11734328
申请日：2007-04-12
申请人： Byoung W. Min , Dharmesh Jawarani
发明人： Byoung W. Min , Dharmesh Jawarani
IPC分类号： H01L21/84
CPC分类号： H01L29/78615 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.
摘要翻译：提供了一种包括提供衬底和提供覆盖衬底的绝缘层的方法。该方法还包括提供包括覆盖绝缘层的主体材料的主体区域。所述方法还包括形成覆盖绝缘层的至少一个晶体管，所述至少一个晶体管具有源极，漏极和具有侧壁间隔物的栅极，所述侧壁间隔物包括围绕栅极的基本上均匀的几何形状，所述栅极覆盖身体区域。所述方法还包括在所述源极内形成第一硅化物区域和所述漏极内的第二硅化物区域，所述第一硅化物区域具有与所述第二硅化物区域不同的几何形状并且在所述体区域和所述源极之间导电。

8. 发明申请

US20080254586A1 SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF 有权
标题翻译：具有身体接触的SOI半导体器件及其方法
公开(公告)号：US20080254586A1
公开(公告)日：2008-10-16
申请号：US11734328
申请日：2007-04-12
申请人： Byoung W. Min , Dharmesh Jawarani
发明人： Byoung W. Min , Dharmesh Jawarani
IPC分类号： H01L21/336
CPC分类号： H01L29/78615 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.
摘要翻译：提供了一种包括提供衬底和提供覆盖衬底的绝缘层的方法。该方法还包括提供包括覆盖绝缘层的主体材料的主体区域。所述方法还包括形成覆盖绝缘层的至少一个晶体管，所述至少一个晶体管具有源极，漏极和具有侧壁间隔物的栅极，所述侧壁间隔物包括围绕栅极的基本上均匀的几何形状，所述栅极覆盖身体区域。所述方法还包括在所述源极内形成第一硅化物区域和所述漏极内的第二硅化物区域，所述第一硅化物区域具有与所述第二硅化物区域不同的几何形状并且在所述体区域和所述源极之间导电。

9. 发明授权

US06844224B2 Substrate contact in SOI and method therefor 有权
标题翻译： SOI中的衬底接触及其方法
公开(公告)号：US06844224B2
公开(公告)日：2005-01-18
申请号：US10002054
申请日：2001-11-15
申请人： Byoung W. Min
发明人： Byoung W. Min
IPC分类号： H01L21/336 , H01L21/74 , H01L21/768 , H01L29/786 , H01L21/00 , H01L21/84
CPC分类号： H01L21/743 , H01L21/76802 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78648
摘要： A doped area is formed in the silicon substrate layer of a silicon-on-insulator stack including a silicon substrate, an insulator layer and an silicon active layer, by implanting a species through at least the insulator layer. In one embodiment, the silicon active layer is etched and the species are implanted in the silicon substrate through the exposed insulator layer. Thus, a doped region is formed in the silicon substrate under the areas where the silicon active layer was removed. In another embodiment after etching the silicon active layer, a dielectric layer is formed adjacent to the silicon active layer and on the insulator layer. In this embodiment, the species are implanted over the entire wafer through both the silicon active layer and the insulator layer. In both embodiments, the species are implanted before forming a gate electrode of a transistor.
摘要翻译：通过至少通过绝缘体层注入物质，在包括硅衬底，绝缘体层和硅有源层的绝缘体上硅堆叠的硅衬底层中形成掺杂区域。在一个实施例中，蚀刻硅有源层，并且通过暴露的绝缘体层将物质注入到硅衬底中。因此，在除去硅有源层的区域之前的硅衬底中形成掺杂区域。在蚀刻硅有源层之后的另一个实施例中，在硅有源层和绝缘体层上形成电介质层。在该实施例中，通过硅有源层和绝缘体层将物质注入到整个晶片上。在两个实施例中，在形成晶体管的栅电极之前注入物质。

10. 发明授权

US5535066A Automatic monitoring method for a video cassette recorder 失效
标题翻译：录像机的自动监控方法
公开(公告)号：US5535066A
公开(公告)日：1996-07-09
申请号：US144037
申请日：1993-11-01
申请人： Byoung W. Min
发明人： Byoung W. Min
IPC分类号： G11B20/02 , G11B27/10 , G11B27/36 , G11B31/00 , H04N5/44 , H04N5/765 , H04N5/775
CPC分类号： G11B27/36 , H04N5/775 , G11B2220/90 , G11B27/107
摘要： An automatic monitoring method for a video cassette recorder permits an automatic monitoring function to be added to a conventional data processing function provide by a VCR microcomputer. When the user selects an automatic monitoring function by a remote controller, automatic monitoring of a television broadcast is made possible during predetermined intervals under the control of the microcomputer during reproduction of a video cassette tape. Thus, the troublesome procedure of repeatedly manipulating a remote controller key is eliminated so that television broadcast monitoring can be carried out if the user forgets to press the key. The method includes steps for determining whether a video cassette tape within a deck section is being reproduced under the control of the microcomputer, determining whether an automatic monitoring function is turned on after recognizing reproduction of the video cassette tape, determining whether a reproduction period for the video cassette tape has elapsed after recognizing turning-on of the automatic monitoring function, and determining whether a television monitoring period has elapsed.
摘要翻译：用于盒式磁带录像机的自动监视方法允许将自动监视功能添加到由VCR微计算机提供的常规数据处理功能。当用户通过遥控器选择自动监视功能时，可以在盒式录像带再现期间在微计算机的控制下的预定间隔期间自动监视电视广播。因此，消除了重复操作遥控器键的麻烦的过程，使得如果用户忘记按下键，则可以执行电视广播监视。该方法包括以下步骤：确定在微型计算机的控制下是否在甲板区段内的盒式录像带正在再现;在识别出盒式录像带的再现之后，确定是否开启了自动监视功能，确定是否为在识别到自动监视功能的接通之后，并且确定电视监视时段是否已经过去，已经过去了录像带。

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