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1. 发明授权

US06495294B1 Method for manufacturing semiconductor substrate having an epitaxial film in the trench 有权
标题翻译：在沟槽中制造具有外延膜的半导体衬底的方法
公开(公告)号：US06495294B1
公开(公告)日：2002-12-17
申请号：US09696951
申请日：2000-10-27
申请人： Shoichi Yamauchi , Yasushi Urakami , Kunihiro Onoda , Toshio Sakakibara , Yoshinori Otsuka
发明人： Shoichi Yamauchi , Yasushi Urakami , Kunihiro Onoda , Toshio Sakakibara , Yoshinori Otsuka
IPC分类号： H01L2176
CPC分类号： H01L29/0634 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02658 , H01L21/02661 , H01L21/743 , H01L21/761 , H01L29/045
摘要： A trench is formed in a silicon substrate, and an epitaxial film is formed on the substrate and in the trench. After a part of the epitaxial film formed around an opening portion of the trench is etched, another epitaxial film is formed on the substrate and in the trench. Accordingly, the trench can be filled with the epitaxial films completely. Then, the surface of the substrate is flattened.
摘要翻译：在硅衬底中形成沟槽，并且在衬底和沟槽中形成外延膜。在蚀刻形成在沟槽的开口部分周围的外延膜的一部分之后，在衬底和沟槽中形成另外的外延膜。因此，沟槽可以完全被外延膜填充。然后，使基板的表面变平。

2. 发明授权

US06406982B2 Method of improving epitaxially-filled trench by smoothing trench prior to filling 有权
标题翻译：通过在填充之前平滑沟槽来改善外延填充沟槽的方法
公开(公告)号：US06406982B2
公开(公告)日：2002-06-18
申请号：US09870705
申请日：2001-06-01
申请人： Yasushi Urakami , Shoichi Yamauchi , Toshio Sakakibara , Hitoshi Yamaguchi , Nobuhiro Tsuji
发明人： Yasushi Urakami , Shoichi Yamauchi , Toshio Sakakibara , Hitoshi Yamaguchi , Nobuhiro Tsuji
IPC分类号： H01L2120
CPC分类号： H01L21/763 , H01L21/30608 , H01L21/761
摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.
摘要翻译：通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。然后，蚀刻掩模的开口部分的边缘部分，使得其开口宽度比沟槽的宽度宽。之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。然后，沟槽填充有外延膜。之后，对该外延膜进行研磨，得到半导体装置的半导体基板。

3. 发明授权

US06191007B1 Method for manufacturing a semiconductor substrate 失效
标题翻译：半导体基板的制造方法
公开(公告)号：US06191007B1
公开(公告)日：2001-02-20
申请号：US09066971
申请日：1998-04-28
申请人： Masaki Matsui , Shoichi Yamauchi , Hisayoshi Ohshima , Kunihiro Onoda , Akiyoshi Asai , Takanari Sasaya , Takeshi Enya , Jun Sakakibara
发明人： Masaki Matsui , Shoichi Yamauchi , Hisayoshi Ohshima , Kunihiro Onoda , Akiyoshi Asai , Takanari Sasaya , Takeshi Enya , Jun Sakakibara
IPC分类号： H01L21331
CPC分类号： H01L21/84 , H01L21/02667 , H01L21/2022 , H01L21/76243 , H01L21/76254 , H01L21/76264 , H01L21/76267 , H01L21/76275 , H01L21/76281 , H01L21/76283 , H01L2221/68363
摘要： Methods for manufacturing semiconductor substrates in which a semiconductor layer for forming semiconductor device therein is formed on a supporting substrate with an insulating film interposed between, with which in forming the semiconductor layer on a substrate on which a buried pattern structure has been formed it is possible to greatly increase the film thickness uniformity of the semiconductor layer and the film thickness controllability, particularly when the semiconductor layer is being formed as an extremely thin film. As a result, it is possible to achieve improved quality and characteristics of the semiconductor substrates and make possible the deployment of such semiconductor substrates to various uses.
摘要翻译：制造半导体衬底的方法，其中半导体器件用于形成半导体器件的半导体层形成在支撑衬底上，绝缘膜介于其之间，在形成掩埋图案结构的衬底上形成半导体层是可能的大大增加了半导体层的膜厚均匀性和膜厚可控性，特别是当半导体层被形成为极薄膜时。结果，可以实现半导体衬底的改进的质量和特性，并且可以将这种半导体衬底部署到各种用途上。

4. 发明授权

US06251754B1 Semiconductor substrate manufacturing method 失效
标题翻译：半导体衬底制造方法
公开(公告)号：US06251754B1
公开(公告)日：2001-06-26
申请号：US09074384
申请日：1998-05-08
申请人： Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Shoichi Yamauchi
发明人： Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Shoichi Yamauchi
IPC分类号： H01L2120
CPC分类号： H01L21/76254
摘要： The invention provides a number of semiconductor substrate manufacturing methods with which, in manufacturing a semiconductor substrate having a semiconductor layer in an insulated state on a supporting substrate, it is possible to obtain a thick semiconductor layer with a simple process and cheaply while reducing impurity contamination of the semiconductor layer to a minimum. One of these methods includes a defective layer forming step of carrying out ion implantation to a predetermined depth from the surface of a base substrate to partition off a monocrystalline thin film layer at the surface of the base substrate by a defective layer formed by implanted ions, a semiconductor film forming step of forming a monocrystalline semiconductor film of a predetermined thickness on the monocrystalline thin film layer, a laminating step of laminating the base substrate by the surface of the monocrystalline semiconductor film to the supporting substrate, and a detaching step of detaching the base substrate laminated to the supporting substrate at the defective layer.
摘要翻译：本发明提供了许多半导体衬底制造方法，在制造具有在支撑衬底上具有绝缘状态的半导体层的半导体衬底的情况下，可以以简单的工艺获得厚半导体层并且在降低杂质污染的同时廉价的半导体层。这些方法之一包括从基底表面进行离子注入到预定深度的缺陷层形成步骤，以通过由注入离子形成的缺陷层在基底基板的表面分隔单晶薄膜层，在单晶薄膜层上形成预定厚度的单晶半导体膜的半导体膜形成步骤，通过单晶半导体膜的表面将基底基板层压到支撑基板上的层压步骤，以及将基板基底基板层叠到不良层的支撑基板。

5. 发明授权

US06642577B2 Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same 有权
标题翻译：包括功率MOSFET和外围设备的半导体器件及其制造方法
公开(公告)号：US06642577B2
公开(公告)日：2003-11-04
申请号：US09804024
申请日：2001-03-13
申请人： Shoichi Yamauchi , Yasushi Urakami
发明人： Shoichi Yamauchi , Yasushi Urakami
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L27/088 , H01L29/4232 , H01L29/4238 , H01L29/78 , H01L29/7801 , H01L29/7813 , H01L29/7823
摘要： First and second trenches are formed on an n+ type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An n− type epitaxial film, a p type epitaxial film, and an n+ type epitaxial film are deposited on the substrate and in the trenches, and then flattening is performed. As a result, an n− type region is provided in the second trench of the peripheral device formation region. Then, a p type well layer is formed in the n− type region by ion-implantation. Accordingly, a power MOSFET and a peripheral device can been formed at the power MOSFET formation region and the peripheral device formation region easily.
摘要翻译：第一和第二沟槽分别在功率MOSFET形成区域和外围器件形成区域的n +型衬底上形成。在衬底上和沟槽中沉积n型外延膜，p型外延膜和n +型外延膜，然后进行平坦化。结果，在外围器件形成区域的第二沟槽中提供n +型区域。然后，通过离子注入在n +型区域中形成p型阱层。因此，能够容易地在功率MOSFET形成区域和外围器件形成区域形成功率MOSFET和外围器件。

6. 发明授权

US06534380B1 Semiconductor substrate and method of manufacturing the same 失效
标题翻译：半导体衬底及其制造方法
公开(公告)号：US06534380B1
公开(公告)日：2003-03-18
申请号：US09116956
申请日：1998-07-17
申请人： Shoichi Yamauchi , Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Tadao Ooka , Akitoshi Yamanaka , Toshifumi Izumi
发明人： Shoichi Yamauchi , Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Tadao Ooka , Akitoshi Yamanaka , Toshifumi Izumi
IPC分类号： H01L2130
CPC分类号： H01L21/76254 , Y10S438/96
摘要： Before a semiconductor substrate and a base substrate is directly bonded to one another, in a protective film removing step, a contamination protective film formed on the semiconductor substrate to protect it from contamination during an ion implanting step is removed. Consequently, even when flatness of the contamination protective film is degraded during the ion implanting step or even when contaminants remain in a segregated state in the vicinity of the surface of the contamination protective film, the state of the bonding between the semiconductor substrate and the base substrate after the bonding step can be made uniform over the entire area of the bonding. As a result, a high-quality semiconductor substrate can be manufactured at low cost.
摘要翻译：在半导体基板和基底基板彼此直接接合之前，在保护膜去除步骤中，去除了在离子注入步骤期间形成在半导体衬底上以防止其污染的污染保护膜。因此，即使当在离子注入步骤期间污染保护膜的平坦度劣化时，或者甚至当污染保护膜表面附近的污染物保持分离状态时，半导体衬底和基底之间的接合状态接合步骤之后的基板可以在结合的整个区域上均匀。结果，可以以低成本制造高质量的半导体衬底。

7. 发明授权

US07063751B2 Semiconductor substrate formed by epitaxially filling a trench in a semiconductor substrate with a semiconductor material after smoothing the surface and rounding the corners 有权
标题翻译：半导体衬底通过在使表面平滑并使其四舍五入之后用半导体材料外延地填充半导体衬底中的沟槽而形成
公开(公告)号：US07063751B2
公开(公告)日：2006-06-20
申请号：US10132298
申请日：2002-04-26
申请人： Yasushi Urakami , Shoichi Yamauchi , Hitoshi Yamaguchi , Nobuhiro Tsuji
发明人： Yasushi Urakami , Shoichi Yamauchi , Hitoshi Yamaguchi , Nobuhiro Tsuji
IPC分类号： H01L29/12 , H01L29/30 , H01L21/20 , H01L21/36 , H01L29/04
CPC分类号： H01L21/763 , H01L21/30608 , H01L21/761
摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.
摘要翻译：通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。然后，蚀刻掩模的开口部分的边缘部分，使得掩模开口宽度的宽度大于沟槽的宽度。之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。然后，沟槽填充有外延膜。之后，抛光外延膜以完成基板。

8. 发明授权

US06495883B2 Trench gate type semiconductor device and method of manufacturing 有权
标题翻译：沟槽型半导体器件及其制造方法
公开(公告)号：US06495883B2
公开(公告)日：2002-12-17
申请号：US10060379
申请日：2002-02-01
申请人： Takumi Shibata , Shoichi Yamauchi , Yasushi Urakami , Toshiyuki Morishita
发明人： Takumi Shibata , Shoichi Yamauchi , Yasushi Urakami , Toshiyuki Morishita
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/4232 , H01L29/42368 , H01L29/4238
摘要： A semiconductor device has a dielectric strength for a gate oxide film at a trench bottom that is higher than that of side walls used for channels. An n+0 type substrate 1 having substrate plane orientation of (110) is prepared, and the side walls of a trench where channels are formed are in (100) planes. The other, non-channel forming, side walls of the trench are in (110) planes. Thus, the growth rate of the gate oxide film 7 in the non-channel forming side walls and the trench bottom is faster than that in the channel forming side walls. As a result, the film thickness at the non-channel-forming side walls and the trench bottom is greater than that of the channel-forming side walls. Accordingly, the device has high mobility, and there is no drop of dielectric strength due to partial reduction of the thickness of the gate oxide film 7. This achieves both a reduction of the ON resistance and an increase in the dielectric strength of the semiconductor device.
摘要翻译：半导体器件在沟槽底部具有比用于沟道的侧壁高的栅极氧化膜的介电强度。制备具有（110）基板平面取向的n + 0型基板1，并且形成通道的沟槽的侧壁在（100）平面中。沟槽的另一个非通道形成侧壁在（110）平面中。因此，非通道形成侧壁和沟槽底部中的栅极氧化膜7的生长速度比形成沟道的侧壁的生长速度快。结果，在非沟道形成侧壁和沟槽底部处的膜厚度大于沟道形成侧壁的膜厚度。因此，器件具有高迁移率，并且由于栅极氧化膜7的厚度的部分减小而不会降低介电强度。这实现了导通电阻的降低和半导体器件的介电强度的增加。

9. 发明授权

US09174877B2 Colored translucent zirconia sintered body, its production process and its use 有权
标题翻译：彩色半透明氧化锆烧结体，其生产工艺及其用途
公开(公告)号：US09174877B2
公开(公告)日：2015-11-03
申请号：US13883151
申请日：2011-11-04
申请人： Shoichi Yamauchi , Isao Yamashita , Koji Tsukuma
发明人： Shoichi Yamauchi , Isao Yamashita , Koji Tsukuma
IPC分类号： C04B35/486 , C04B35/49 , C04B35/488 , C04B35/645
CPC分类号： C04B35/49 , C04B35/486 , C04B35/488 , C04B35/6455 , C04B2235/3224 , C04B2235/3225 , C04B2235/3232 , C04B2235/3237 , C04B2235/3239 , C04B2235/3241 , C04B2235/3262 , C04B2235/3272 , C04B2235/3275 , C04B2235/3279 , C04B2235/3281 , C04B2235/5409 , C04B2235/652 , C04B2235/656 , C04B2235/6565 , C04B2235/661 , C04B2235/663 , C04B2235/762 , C04B2235/77 , C04B2235/786 , C04B2235/80 , C04B2235/96 , C04B2235/963 , C04B2235/9653 , C04B2235/9661
摘要： A colored translucent zirconia sintered body contains a transition metal element as a coloring agent, having a clear color tone and high transparency, and being excellent in both design properties and esthetic properties, and its production process. A colored translucent zirconia sintered body includes yttria in an amount of at least 6 mol % and at most 15 mol % and at least one member selected from the group consisting of iron, nickel, manganese, cobalt, chromium, copper and vanadium in an amount of at least 0.02 mol % and at most 0.5 mol % as calculated as oxides, and having a porosity of at most 1,000 ppm. The average crystal grain size is preferably at most 60 μm.
摘要翻译：彩色半透明氧化锆烧结体包含过渡金属元素作为着色剂，具有清晰的色调和高透明度，并且具有优异的设计性能和美学特性及其制备方法。彩色半透明氧化锆烧结体包括量为至少6mol％且至多15mol％的氧化钇和至少一种选自铁，镍，锰，钴，铬，铜和钒中的一种，其量为至少0.02mol％和至多0.5mol％，以氧化物计算，并且具有至多1,000ppm的孔隙率。平均结晶粒径优选为60μm以下。

10. 发明授权

US08835276B2 Method for manufacturing semiconductor substrate 有权
标题翻译：半导体衬底的制造方法
公开(公告)号：US08835276B2
公开(公告)日：2014-09-16
申请号：US12964141
申请日：2010-12-09
申请人： Syouji Nogami , Tomonori Yamaoka , Shoichi Yamauchi , Nobuhiro Tsuji , Toshiyuki Morishita
发明人： Syouji Nogami , Tomonori Yamaoka , Shoichi Yamauchi , Nobuhiro Tsuji , Toshiyuki Morishita
IPC分类号： H01L21/76 , H01L23/544 , H01L29/06 , H01L29/66 , H01L21/02
CPC分类号： H01L21/30604 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/02664 , H01L21/308 , H01L23/544 , H01L29/0634 , H01L29/66712 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N−-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.
摘要翻译：提供了一种半导体衬底，其中形成了即使在通过外延膜的平坦化形成杂质扩散层之后也可以用于取向的对准标记。在N +型衬底的取向区域中形成沟槽。这种沟槽用于在形成N型层之后留下空隙。然后，可以使用形成在N +型衬底中的空隙作为对准标记。因此，可以使用这样的半导体衬底在制造半导体器件的后续步骤中提供对准。因此，能够精确地形成构成半导体装置的各个部件。

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