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1. 发明授权

US06534380B1 Semiconductor substrate and method of manufacturing the same 失效
标题翻译：半导体衬底及其制造方法
公开(公告)号：US06534380B1
公开(公告)日：2003-03-18
申请号：US09116956
申请日：1998-07-17
申请人： Shoichi Yamauchi , Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Tadao Ooka , Akitoshi Yamanaka , Toshifumi Izumi
发明人： Shoichi Yamauchi , Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Tadao Ooka , Akitoshi Yamanaka , Toshifumi Izumi
IPC分类号： H01L2130
CPC分类号： H01L21/76254 , Y10S438/96
摘要： Before a semiconductor substrate and a base substrate is directly bonded to one another, in a protective film removing step, a contamination protective film formed on the semiconductor substrate to protect it from contamination during an ion implanting step is removed. Consequently, even when flatness of the contamination protective film is degraded during the ion implanting step or even when contaminants remain in a segregated state in the vicinity of the surface of the contamination protective film, the state of the bonding between the semiconductor substrate and the base substrate after the bonding step can be made uniform over the entire area of the bonding. As a result, a high-quality semiconductor substrate can be manufactured at low cost.
摘要翻译：在半导体基板和基底基板彼此直接接合之前，在保护膜去除步骤中，去除了在离子注入步骤期间形成在半导体衬底上以防止其污染的污染保护膜。因此，即使当在离子注入步骤期间污染保护膜的平坦度劣化时，或者甚至当污染保护膜表面附近的污染物保持分离状态时，半导体衬底和基底之间的接合状态接合步骤之后的基板可以在结合的整个区域上均匀。结果，可以以低成本制造高质量的半导体衬底。

2. 发明授权

US06191007B1 Method for manufacturing a semiconductor substrate 失效
标题翻译：半导体基板的制造方法
公开(公告)号：US06191007B1
公开(公告)日：2001-02-20
申请号：US09066971
申请日：1998-04-28
申请人： Masaki Matsui , Shoichi Yamauchi , Hisayoshi Ohshima , Kunihiro Onoda , Akiyoshi Asai , Takanari Sasaya , Takeshi Enya , Jun Sakakibara
发明人： Masaki Matsui , Shoichi Yamauchi , Hisayoshi Ohshima , Kunihiro Onoda , Akiyoshi Asai , Takanari Sasaya , Takeshi Enya , Jun Sakakibara
IPC分类号： H01L21331
CPC分类号： H01L21/84 , H01L21/02667 , H01L21/2022 , H01L21/76243 , H01L21/76254 , H01L21/76264 , H01L21/76267 , H01L21/76275 , H01L21/76281 , H01L21/76283 , H01L2221/68363
摘要： Methods for manufacturing semiconductor substrates in which a semiconductor layer for forming semiconductor device therein is formed on a supporting substrate with an insulating film interposed between, with which in forming the semiconductor layer on a substrate on which a buried pattern structure has been formed it is possible to greatly increase the film thickness uniformity of the semiconductor layer and the film thickness controllability, particularly when the semiconductor layer is being formed as an extremely thin film. As a result, it is possible to achieve improved quality and characteristics of the semiconductor substrates and make possible the deployment of such semiconductor substrates to various uses.
摘要翻译：制造半导体衬底的方法，其中半导体器件用于形成半导体器件的半导体层形成在支撑衬底上，绝缘膜介于其之间，在形成掩埋图案结构的衬底上形成半导体层是可能的大大增加了半导体层的膜厚均匀性和膜厚可控性，特别是当半导体层被形成为极薄膜时。结果，可以实现半导体衬底的改进的质量和特性，并且可以将这种半导体衬底部署到各种用途上。

3. 发明授权

US06251754B1 Semiconductor substrate manufacturing method 失效
标题翻译：半导体衬底制造方法
公开(公告)号：US06251754B1
公开(公告)日：2001-06-26
申请号：US09074384
申请日：1998-05-08
申请人： Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Shoichi Yamauchi
发明人： Hisayoshi Ohshima , Masaki Matsui , Kunihiro Onoda , Shoichi Yamauchi
IPC分类号： H01L2120
CPC分类号： H01L21/76254
摘要： The invention provides a number of semiconductor substrate manufacturing methods with which, in manufacturing a semiconductor substrate having a semiconductor layer in an insulated state on a supporting substrate, it is possible to obtain a thick semiconductor layer with a simple process and cheaply while reducing impurity contamination of the semiconductor layer to a minimum. One of these methods includes a defective layer forming step of carrying out ion implantation to a predetermined depth from the surface of a base substrate to partition off a monocrystalline thin film layer at the surface of the base substrate by a defective layer formed by implanted ions, a semiconductor film forming step of forming a monocrystalline semiconductor film of a predetermined thickness on the monocrystalline thin film layer, a laminating step of laminating the base substrate by the surface of the monocrystalline semiconductor film to the supporting substrate, and a detaching step of detaching the base substrate laminated to the supporting substrate at the defective layer.
摘要翻译：本发明提供了许多半导体衬底制造方法，在制造具有在支撑衬底上具有绝缘状态的半导体层的半导体衬底的情况下，可以以简单的工艺获得厚半导体层并且在降低杂质污染的同时廉价的半导体层。这些方法之一包括从基底表面进行离子注入到预定深度的缺陷层形成步骤，以通过由注入离子形成的缺陷层在基底基板的表面分隔单晶薄膜层，在单晶薄膜层上形成预定厚度的单晶半导体膜的半导体膜形成步骤，通过单晶半导体膜的表面将基底基板层压到支撑基板上的层压步骤，以及将基板基底基板层叠到不良层的支撑基板。

4. 发明授权

US06495294B1 Method for manufacturing semiconductor substrate having an epitaxial film in the trench 有权
标题翻译：在沟槽中制造具有外延膜的半导体衬底的方法
公开(公告)号：US06495294B1
公开(公告)日：2002-12-17
申请号：US09696951
申请日：2000-10-27
申请人： Shoichi Yamauchi , Yasushi Urakami , Kunihiro Onoda , Toshio Sakakibara , Yoshinori Otsuka
发明人： Shoichi Yamauchi , Yasushi Urakami , Kunihiro Onoda , Toshio Sakakibara , Yoshinori Otsuka
IPC分类号： H01L2176
CPC分类号： H01L29/0634 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02658 , H01L21/02661 , H01L21/743 , H01L21/761 , H01L29/045
摘要： A trench is formed in a silicon substrate, and an epitaxial film is formed on the substrate and in the trench. After a part of the epitaxial film formed around an opening portion of the trench is etched, another epitaxial film is formed on the substrate and in the trench. Accordingly, the trench can be filled with the epitaxial films completely. Then, the surface of the substrate is flattened.
摘要翻译：在硅衬底中形成沟槽，并且在衬底和沟槽中形成外延膜。在蚀刻形成在沟槽的开口部分周围的外延膜的一部分之后，在衬底和沟槽中形成另外的外延膜。因此，沟槽可以完全被外延膜填充。然后，使基板的表面变平。

5. 发明授权

US09174877B2 Colored translucent zirconia sintered body, its production process and its use 有权
标题翻译：彩色半透明氧化锆烧结体，其生产工艺及其用途
公开(公告)号：US09174877B2
公开(公告)日：2015-11-03
申请号：US13883151
申请日：2011-11-04
申请人： Shoichi Yamauchi , Isao Yamashita , Koji Tsukuma
发明人： Shoichi Yamauchi , Isao Yamashita , Koji Tsukuma
IPC分类号： C04B35/486 , C04B35/49 , C04B35/488 , C04B35/645
CPC分类号： C04B35/49 , C04B35/486 , C04B35/488 , C04B35/6455 , C04B2235/3224 , C04B2235/3225 , C04B2235/3232 , C04B2235/3237 , C04B2235/3239 , C04B2235/3241 , C04B2235/3262 , C04B2235/3272 , C04B2235/3275 , C04B2235/3279 , C04B2235/3281 , C04B2235/5409 , C04B2235/652 , C04B2235/656 , C04B2235/6565 , C04B2235/661 , C04B2235/663 , C04B2235/762 , C04B2235/77 , C04B2235/786 , C04B2235/80 , C04B2235/96 , C04B2235/963 , C04B2235/9653 , C04B2235/9661
摘要： A colored translucent zirconia sintered body contains a transition metal element as a coloring agent, having a clear color tone and high transparency, and being excellent in both design properties and esthetic properties, and its production process. A colored translucent zirconia sintered body includes yttria in an amount of at least 6 mol % and at most 15 mol % and at least one member selected from the group consisting of iron, nickel, manganese, cobalt, chromium, copper and vanadium in an amount of at least 0.02 mol % and at most 0.5 mol % as calculated as oxides, and having a porosity of at most 1,000 ppm. The average crystal grain size is preferably at most 60 μm.
摘要翻译：彩色半透明氧化锆烧结体包含过渡金属元素作为着色剂，具有清晰的色调和高透明度，并且具有优异的设计性能和美学特性及其制备方法。彩色半透明氧化锆烧结体包括量为至少6mol％且至多15mol％的氧化钇和至少一种选自铁，镍，锰，钴，铬，铜和钒中的一种，其量为至少0.02mol％和至多0.5mol％，以氧化物计算，并且具有至多1,000ppm的孔隙率。平均结晶粒径优选为60μm以下。

6. 发明授权

US08835276B2 Method for manufacturing semiconductor substrate 有权
标题翻译：半导体衬底的制造方法
公开(公告)号：US08835276B2
公开(公告)日：2014-09-16
申请号：US12964141
申请日：2010-12-09
申请人： Syouji Nogami , Tomonori Yamaoka , Shoichi Yamauchi , Nobuhiro Tsuji , Toshiyuki Morishita
发明人： Syouji Nogami , Tomonori Yamaoka , Shoichi Yamauchi , Nobuhiro Tsuji , Toshiyuki Morishita
IPC分类号： H01L21/76 , H01L23/544 , H01L29/06 , H01L29/66 , H01L21/02
CPC分类号： H01L21/30604 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/02664 , H01L21/308 , H01L23/544 , H01L29/0634 , H01L29/66712 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N−-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.
摘要翻译：提供了一种半导体衬底，其中形成了即使在通过外延膜的平坦化形成杂质扩散层之后也可以用于取向的对准标记。在N +型衬底的取向区域中形成沟槽。这种沟槽用于在形成N型层之后留下空隙。然后，可以使用形成在N +型衬底中的空隙作为对准标记。因此，可以使用这样的半导体衬底在制造半导体器件的后续步骤中提供对准。因此，能够精确地形成构成半导体装置的各个部件。

7. 发明授权

US07776710B2 Manufacturing method of semiconductor wafer having a trench structure and epitaxial layer 有权
标题翻译：具有沟槽结构和外延层的半导体晶片的制造方法
公开(公告)号：US07776710B2
公开(公告)日：2010-08-17
申请号：US10562235
申请日：2005-03-31
申请人： Syouji Nogami , Yukichi Horioka , Shoichi Yamauchi
发明人： Syouji Nogami , Yukichi Horioka , Shoichi Yamauchi
IPC分类号： H01L21/76
CPC分类号： H01L21/02063 , H01L21/02068 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/2205 , H01L29/0634
摘要： A resistivity of an epitaxial layer in a trench is changed in a stepwise manner by reducing a quantity of an impurity diffused into the epitaxial layer in the trench from a semiconductor wafer in a stepwise manner, thereby suppressing an influence of auto-doping from the semiconductor wafer.An epitaxial layer 17 is grown in a trench 16 of a semiconductor wafer 10 having a trench structure by gradually reducing a temperature in a temperature in the range of 400 to 1150° C. by a vapor growth method while supplying a silane gas as a raw material gas, thereby filling the epitaxial layer 17 in the trench 16.
摘要翻译：沟槽中的外延层的电阻率通过逐步地从半导体晶片减少从沟槽中扩散到外延层中的杂质的量来逐步地改变，从而抑制半导体自动掺杂的影响晶圆。在具有沟槽结构的半导体晶片10的沟槽16中，通过气相生长法逐渐降低温度在400〜1150℃的范围内的温度而生长外延层17，同时以硅原料从而填充沟槽16中的外延层17。

8. 发明申请

US20090273102A1 Semiconductor Substrate and Method for Manufacturing the Same 审中-公开
标题翻译：半导体基板及其制造方法
公开(公告)号：US20090273102A1
公开(公告)日：2009-11-05
申请号：US12089497
申请日：2006-10-05
申请人： Syouji Nogami , Tomonori Yamaoka , Shoichi Yamauchi , Nobuhiro Tsuji , Toshiyuki Morishita
发明人： Syouji Nogami , Tomonori Yamaoka , Shoichi Yamauchi , Nobuhiro Tsuji , Toshiyuki Morishita
IPC分类号： H01L23/544 , H01L21/308
CPC分类号： H01L21/30604 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/02664 , H01L21/308 , H01L23/544 , H01L29/0634 , H01L29/66712 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film.A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N−-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.
摘要翻译：提供了一种半导体衬底，其中形成了即使在通过外延膜的平坦化形成杂质扩散层之后也可用于分配的对准标记。在N +型衬底1的取向区域中形成沟槽11.在形成N型层2之后，该沟槽11用于留下空隙3.然后，形成在N +型衬底中的空隙3 1可用作对准标记。因此，可以使用这样的半导体衬底在制造半导体器件的后续步骤中提供对准。因此，能够精确地形成构成半导体装置的各个部件。

9. 发明申请

US20070238271A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070238271A1
公开(公告)日：2007-10-11
申请号：US11806862
申请日：2007-06-05
申请人： Shoichi Yamauchi , Yoshiyuki Hattori , Kyoko Okada
发明人： Shoichi Yamauchi , Yoshiyuki Hattori , Kyoko Okada
IPC分类号： H01L21/20
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.
摘要翻译：具有SJ结构的半导体器件具有比电池区域的耐电压更高的耐受电压的周边区域。在周边区域的半导体层中形成有包含第二导电型杂质的半导体上层和包含第一导电型杂质的半导体下层，该第一导电型杂质的浓度低于构成该单元区域组合的第一部分区域。在半导体上层的表面上形成场氧化物层。

10. 发明申请

US20070013412A1 Semiconductor device having super junction structure and method for manufacturing the same 有权
标题翻译：具有超结结构的半导体器件及其制造方法
公开(公告)号：US20070013412A1
公开(公告)日：2007-01-18
申请号：US11472547
申请日：2006-06-22
申请人： Shoichi Yamauchi , Tomoatsu Makino , Makoto Kuwahara , Yoshiyuki Hattori
发明人： Shoichi Yamauchi , Tomoatsu Makino , Makoto Kuwahara , Yoshiyuki Hattori
IPC分类号： H03K19/091
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a cell region; a terminal region; a lower semiconductor layer; a intermediate semiconductor layer on the lower semiconductor layer including a super junction structure; a terminal upper semiconductor layer on the intermediate semiconductor layer; a terminal contact semiconductor region on a surface portion of the terminal upper semiconductor layer adjacent to the cell region; an insulation layer on the terminal upper semiconductor layer having a first part adjacent to the cell region with a small thickness and a second part adjacent to the first part with a large thickness; and a conductive layer in the cell region and a part of the terminal region, the conductive layer extending from the cell region to the part of the terminal region beyond the first part of the insulation layer.
摘要翻译：半导体器件包括：单元区域; 终端区域下半导体层; 包括超级结结构的下半导体层上的中间半导体层; 中间半导体层上的端子上半导体层; 在所述端子上半导体层的与所述单元区域相邻的表面部分上的端子接触半导体区域; 端子上半导体层上的绝缘层具有邻近具有小厚度的单元区域的第一部分和与厚度较大的第一部分相邻的第二部分; 以及在所述单元区域和所述端子区域的一部分中的导电层，所述导电层从所述单元区域延伸到所述绝缘层的所述第一部分之外的所述端子区域的所述部分。

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