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1. 发明授权

US5831870A Method and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimation 失效
标题翻译：用于表征集成电路内的互连数据以便于寄生电容估计的方法和系统
公开(公告)号：US5831870A
公开(公告)日：1998-11-03
申请号：US726722
申请日：1996-10-07
申请人： Alan Charles Folta , Sharad Mehrotra , Parsotam Trikam Patel , Paul Gerard Villarrubia
发明人： Alan Charles Folta , Sharad Mehrotra , Parsotam Trikam Patel , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area. By utilizing these recorded information, the parasitic capacitance of the integrated circuit can be estimated more efficiently.
摘要翻译：公开了一种用于表征集成电路内的互连数据以便于寄生电容估计的方法和系统。集成电路通常包括基底层和几个金属层。根据本发明的方法和系统，首先在集成电路内识别互连线的重叠区域。作为多边形的该重叠区域可以形成在基板层和多个金属层之一中的至少一个互连线之间。重叠区域也可以形成在两个互连线之间，每个布线在几个金属层中的不同的一个中。然后记录重叠区域的网络名称。最后，针对重叠区域内的每个互连线，记录金属层内的互连线的网络名称，该网络位于重叠区域内的互连线的相同电平以及与重叠区域的每一侧相关联的距离。通过利用这些记录的信息，可以更有效地估计集成电路的寄生电容。

2. 发明授权

US06510540B1 Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips 失效
标题翻译：数字芯片串扰分析中减少悲观的窗口化机制
公开(公告)号：US06510540B1
公开(公告)日：2003-01-21
申请号：US09640540
申请日：2000-08-17
申请人： Byron Lee Krauter , Sharad Mehrotra , Jonathan Humphrey Saxman , Paul Gerard Villarrubia , David J. Widiger
发明人： Byron Lee Krauter , Sharad Mehrotra , Jonathan Humphrey Saxman , Paul Gerard Villarrubia , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： This invention reduces pessimism in cross talk analysis of digital circuits by combining only the peak noises from aggressor nets that can switch simultaneously during the time interval when the downstream receiving latch can sample the errant data. This is done by, first, determining aggressor switching windows and victim sensitivity windows. These windows are then used to determine which combination of noise sources can temporally align so as to cause the greatest noise within the victim sensitivity window.
摘要翻译：本发明通过仅在来自下游接收锁存器可以对错误数据进行采样的时间间隔期间同时切换的来自侵略者网络的峰值噪声组合来减少数字电路的串扰分析中的悲观情绪。这是通过首先确定侵略者切换窗口和受害者敏感性窗口来完成的。然后，这些窗口用于确定噪声源的哪个组合可以在时间上对齐，以便在受害者敏感度窗口内引起最大的噪声。

3. 发明授权

US5838582A Method and system for performing parasitic capacitance estimations on interconnect data within an integrated circuit 失效
标题翻译：用于对集成电路内的互连数据执行寄生电容估计的方法和系统
公开(公告)号：US5838582A
公开(公告)日：1998-11-17
申请号：US726720
申请日：1996-10-07
申请人： Sharad Mehrotra , Paul Gerard Villarrubia
发明人： Sharad Mehrotra , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for providing parasitic capacitance estimation on interconnect data for an integrated circuit is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, a center wire within one of the several metal layers is first identified. Then, a first capacitance value between a first wire and the center wire as well as a second capacitance value between a second wire and the center wire are determined. The first wire, the second wire, and the center wire are in the same metal layer. Next, a third capacitance value between a third wire and the center wire is determined. This third wire is in a metal layer located directly beneath the center wire. Finally, a fourth capacitance value between a fourth wire and the center wire is determined. The fourth wire is in a metal layer located directly above the center wire. If there are more than one wire within the metal layer directly above the center wire, the fourth capacitance value is distributed among all these wires. By so doing, the total parasitic capacitance for the center wire can be estimated by utilizing the first capacitance value, the second capacitance value, the third capacitance value, and the fourth capacitance value or the distributed fourth capacitance values.
摘要翻译：公开了一种用于为集成电路的互连数据提供寄生电容估计的方法和系统。集成电路通常包括基底层和几个金属层。根据本发明的方法和系统，首先确定几个金属层之一内的中心线。然后，确定第一线和中心线之间的第一电容值以及第二线和中心线之间的第二电容值。第一线，第二线和中心线在相同的金属层中。接下来，确定第三线和中心线之间的第三电容值。该第三根导线位于中心线正下方的金属层中。最后，确定第四线和中心线之间的第四电容值。第四根导线位于中心线正上方的金属层中。如果在中心线正上方的金属层内存在多根线，则第四电容值分布在所有这些线之间。通过这样做，可以通过利用第一电容值，第二电容值，第三电容值和第四电容值或分布的第四电容值来估计中心线的总寄生电容。

4. 发明授权

US6086238A Method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation 失效
标题翻译：用于寄生电容估计的集成电路布局中的形状处理方法和系统
公开(公告)号：US6086238A
公开(公告)日：2000-07-11
申请号：US726721
申请日：1996-10-07
申请人： Sharad Mehrotra , Paul Gerard Villarrubia , David James Widiger
发明人： Sharad Mehrotra , Paul Gerard Villarrubia , David James Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation is disclosed. In accordance with the method and system of the present invention, a set of coordinates of an overlapping region formed by at least one interconnect is first identified. Subsequently, each metal layer present within the overlapping region is classified. Each interconnect edge present on each side of the overlapping region is then determined. Finally, a neighbor in a direction perpendicular to each side of the overlapping region is determined. By so doing, the parasitic capacitance between the overlapping region and its determined neighbors can be evaluated.
摘要翻译：公开了一种用于寄生电容估计的集成电路布局内的形状处理方法和系统。根据本发明的方法和系统，首先确定由至少一个互连形成的重叠区域的一组坐标。随后，重叠区域内存在的各金属层被分类。然后确定存在于重叠区域的每一侧上的每个互连边缘。最后，确定在与重叠区域的每一侧垂直的方向上的邻居。通过这样做，可以评估重叠区域与其确定的邻居之间的寄生电容。

5. 发明授权

US06996512B2 Practical methodology for early buffer and wire resource allocation 失效
公开(公告)号：US06996512B2
公开(公告)日：2006-02-07
申请号：US09838429
申请日：2001-04-19
申请人： Charles Jay Alpert , Jiang Hu , Paul Gerard Villarrubia
发明人： Charles Jay Alpert , Jiang Hu , Paul Gerard Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072
摘要： A method, system, and computer program product for allocating buffer and wire placement in an integrated circuit design is provided. In one embodiment, the surface of a integrated circuit design is represented as a tile graph. Allocation of buffer locations for selected tiles in the tile graph is then received and nets are routed between associated sources and sinks. Buffer locations within selected tiles are then selectively assigned based upon buffer needs of the nets, wherein the nets are routed through selected tiles and assigned buffer locations using a cost minimization algorithm.

6. 发明申请

US20090064074A1 SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DIFFUSION BASED CELL PLACEMENT MIGRATION 有权
标题翻译：用于基于扩散的电池放置移动的系统和计算机程序产品
公开(公告)号：US20090064074A1
公开(公告)日：2009-03-05
申请号：US12264619
申请日：2008-11-04
申请人： Charles Jay Alpert , Haoxing Ren , Paul Gerard Villarrubia
发明人： Charles Jay Alpert , Haoxing Ren , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and computer program product for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.
摘要翻译：一种用于在集成电路设计中用于单元放置的系统和计算机程序产品，其使用从密度值确定的计算的扩散速度，以便重新定位单元直到单元布置将密度降低到低于预定阈值。该方法用于控制不同细胞的运动，以在细胞放置合法化之前降低细胞的密度。

7. 发明授权

US07047163B1 Method and apparatus for applying fine-grained transforms during placement synthesis interaction 失效
标题翻译：在放置合成相互作用期间应用细粒度变换的方法和装置
公开(公告)号：US07047163B1
公开(公告)日：2006-05-16
申请号：US09524408
申请日：2000-03-13
申请人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
发明人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
IPC分类号： G06F17/10 , G06F7/60 , G06F15/18 , G06G7/00 , G06N3/00
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.
摘要翻译：在设计空间中同时应用用于修改多个域的变换的方法（和系统）包括创建越来越少的粒度位置和网表修改变换的序列。融合设计流程由灵活的机制创建，其中应用细粒度变换的选择组合来优化设计的网表和布局。

8. 发明授权

US07296252B2 Clustering techniques for faster and better placement of VLSI circuits 有权
标题翻译：用于更快更好地布置VLSI电路的聚类技术
公开(公告)号：US07296252B2
公开(公告)日：2007-11-13
申请号：US10996293
申请日：2004-11-22
申请人： Charles Jay Alpert , Gi-Joon Nam , Sherief Mohamed Reda , Paul Gerard Villarrubia
发明人： Charles Jay Alpert , Gi-Joon Nam , Sherief Mohamed Reda , Paul Gerard Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F17/50
摘要： A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects into a cluster based on the clustering scores, partitioning the objects as clustered and ungrouping the cluster after partitioning. The pair of objects having the highest clustering score are grouped into the cluster, and the clustering score is directly proportional to the total weight of connections between the two objects in the respective pair. The clustering scores are preferably inserted in a binary heap to identify the highest clustering score. After grouping, the clustering score for any neighboring object of a clustered object is marked to indicate that the clustering score is invalid and must be recalculated. The calculating and grouping are then repeated iteratively based on the previous clustered layout. Cluster growth can be controlled indirectly, or controlled directly by imposing an upper bound on cluster size.
摘要翻译：一种用于通过基于给定对中的两个对象的连接和两个对象的大小的布局来计算布局中的不同对对象的聚类分数来设计集成电路的布局的布局技术，然后将至少一个对对象基于聚类分数进入群集，将对象分区为群集，并在分区后取消分组群集。具有最高聚类分数的一对对象被分组到聚类中，并且聚类分数与相应对中的两个对象之间的连接的总权重成正比。聚类分数优选插入二进制堆中以识别最高聚类分数。分组后，将聚类对象的任何邻近对象的聚类分数标记为表示聚类分数无效并且必须重新计算。然后基于先前的聚类布局迭代地重复计算和分组。群集增长可以间接控制，也可以通过对群集大小施加上限直接控制。

9. 发明授权

US06286007B1 Method and system for efficiently storing and viewing data in a database 失效
标题翻译：在数据库中高效地存储和查看数据的方法和系统
公开(公告)号：US06286007B1
公开(公告)日：2001-09-04
申请号：US09170901
申请日：1998-10-13
申请人： Clinton Frederick Miller , Paul Gerard Villarrubia
发明人： Clinton Frederick Miller , Paul Gerard Villarrubia
IPC分类号： G06F900
CPC分类号： G06F17/30958 , Y10S707/99936 , Y10S707/99942
摘要： A method and system are disclosed for efficiently storing and viewing data in a database. Data is stored in a nested data model which includes a plurality of nodes. A plurality of edges connect the plurality of nodes. Each edge has a unique edge name. A plurality of instances of data objects are associated with the nested data model. Each instance is associated with one of the edges such that the instance is also associated with that edge's name. An instance ordinal is associated with each instance which represents the number of times the edge associated with each instance is encountered during a traversal of the nested data model. The data stored utilizing the nested data model is accessed utilizing the instance ordinal and edge name associated with each of the plurality of instances, such that the data is accessed as being flat without flattening the nested data model.
摘要翻译：公开了一种用于在数据库中有效地存储和查看数据的方法和系统。数据被存储在包括多个节点的嵌套数据模型中。多个边缘连接多个节点。每个边缘都有一个独特的边缘名称。数据对象的多个实例与嵌套数据模型相关联。每个实例与其中一个边缘相关联，使得实例也与该边缘的名称相关联。实例序数与每个实例相关联，表示在遍历嵌套数据模型期间遇到与每个实例相关联的边的次数。使用嵌套数据模型存储的数据使用与多个实例中的每个实例相关联的实例序数和边缘名称被访问，使得数据被访问为平坦而不使嵌套数据模型变平。

10. 发明授权

US06230302B1 Method and system for performing timing analysis on an integrated circuit design 失效
标题翻译：用于对集成电路设计进行定时分析的方法和系统
公开(公告)号：US06230302B1
公开(公告)日：2001-05-08
申请号：US09119271
申请日：1998-07-20
申请人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Alexander Koos Spencer
发明人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Alexander Koos Spencer
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain more accurate timing information about the design. However, at an early stage of the design process, the available physical circuit data are often incomplete, not to mention these preliminary data are usually of a lower quality as far as capability of providing an accurate RC delay and capacitance estimation is concerned. To make the best usage of the preliminary data, the present disclosure describes a method of performing a fleeting timing analysis that can be very useful during an early floor planning stage of the design process when there is no opportunity to buffer or widen any exceptionally long interconnect wires within the IC circuit design. As a result, much faster design turn-around time may be achieved because buffer insertion need not be run for every new pass of the physical circuit design data.
摘要翻译：公开了一种用于对集成电路设计进行定时分析的方法和系统。能够方便地在设计过程的任何阶段对整个IC设计进行时序分析，以便获得关于设计的更准确的时序信息。然而，在设计过程的早期阶段，可用的物理电路数据通常是不完整的，更不用说，就提供准确的RC延迟和电容估计的能力而言，这些初步数据通常质量较差。为了最佳地利用初步数据，本公开描述了一种执行短暂定时分析的方法，其在设计过程的早期楼层规划阶段非常有用，当不存在缓冲或加宽任何特别长的互连电线内IC电路设计。因此，可以实现更快的设计周转时间，因为不需要为物理电路设计数据的每个新的通过运行缓冲器插入。

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