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1. 发明授权

US06510540B1 Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips 失效
标题翻译：数字芯片串扰分析中减少悲观的窗口化机制
公开(公告)号：US06510540B1
公开(公告)日：2003-01-21
申请号：US09640540
申请日：2000-08-17
申请人： Byron Lee Krauter , Sharad Mehrotra , Jonathan Humphrey Saxman , Paul Gerard Villarrubia , David J. Widiger
发明人： Byron Lee Krauter , Sharad Mehrotra , Jonathan Humphrey Saxman , Paul Gerard Villarrubia , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： This invention reduces pessimism in cross talk analysis of digital circuits by combining only the peak noises from aggressor nets that can switch simultaneously during the time interval when the downstream receiving latch can sample the errant data. This is done by, first, determining aggressor switching windows and victim sensitivity windows. These windows are then used to determine which combination of noise sources can temporally align so as to cause the greatest noise within the victim sensitivity window.
摘要翻译：本发明通过仅在来自下游接收锁存器可以对错误数据进行采样的时间间隔期间同时切换的来自侵略者网络的峰值噪声组合来减少数字电路的串扰分析中的悲观情绪。这是通过首先确定侵略者切换窗口和受害者敏感性窗口来完成的。然后，这些窗口用于确定噪声源的哪个组合可以在时间上对齐，以便在受害者敏感度窗口内引起最大的噪声。

2. 发明授权

US06601222B1 Coupled noise estimation and avoidance of noise-failure using global routing information 失效
标题翻译：使用全局路由信息耦合噪声估计和避免噪声故障
公开(公告)号：US06601222B1
公开(公告)日：2003-07-29
申请号：US09687132
申请日：2000-10-13
申请人： Sharad Mehrotra , Parsotam Trikam Patel , David J. Widiger
发明人： Sharad Mehrotra , Parsotam Trikam Patel , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5077
摘要： Disclosed is a method for pre-design estimation of coupling noise and avoidance of coupling noise failures in interconnects. An initial routing of a plurality of nets is estimated utilizing global paths. Then, the worst-case and average-case models for various parameters of each net are evaluated. With these models, a noise analysis is completed by which a determination is made whether coupling noise of any one of the nets is above a threshold level for noise-induced failure (i.e., a noise-failure threshold). When it is determined that the estimated coupling noise of a net falls below the noise-failure threshold, a response mechanism is triggered for later implementation during detailed routing of the nets to prevent the coupling noise from reaching the noise-failure threshold.
摘要翻译：公开了一种用于耦合噪声的预设计估计和避免互连中的耦合噪声故障的方法。使用全局路径来估计多个网络的初始路由。然后，对每个网络的各种参数的最坏情况和平均情况模型进行评估。利用这些模型，完成噪声分析，通过该噪声分析确定任何一个网络的耦合噪声是否高于用于噪声引起的故障（即，噪声失效阈值）的阈值电平。当确定网络的估计耦合噪声低于噪声失效阈值时，在网络的详细路由期间触发响应机制以供稍后实现，以防止耦合噪声达到噪声失效阈值。

3. 发明授权

US06523149B1 Method and system to improve noise analysis performance of electrical circuits 失效
标题翻译：改善电路噪声分析性能的方法和系统
公开(公告)号：US06523149B1
公开(公告)日：2003-02-18
申请号：US09666272
申请日：2000-09-21
申请人： Sharad Mehrotra , Mark W. Wenning , David J. Widiger
发明人： Sharad Mehrotra , Mark W. Wenning , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method, system and apparatus is provided to perform noise analysis of electrical circuits. The method and system partitions an original multi-port circuit to a reduced circuit model having a specific layout configuration. The reduced circuit model may have a variety of configurations. Then an input signal is applied to a first port of the reduced circuit model using the specific layout configuration and an output signal is measured from a second port of the reduced circuit model. The process continues until all input ports which may contribute noise to the circuit are measured and then the results are calculated to determine the total output of simulated noise experienced by the circuit. The calculated output results of the reduced circuit model are then used to determine whether the original circuit is designed to withstand the quantity of noise experienced by the reduced circuit model.
摘要翻译：提供了一种方法，系统和装置来执行电路的噪声分析。该方法和系统将原始多端口电路分为具有特定布局配置的简化电路模型。简化电路模型可以具有各种配置。然后使用特定布局配置将输入信号施加到减小电路模型的第一端口，并且从简化电路模型的第二端口测量输出信号。该过程继续进行，直到可能对电路产生噪声的所有输入端口进行测量，然后计算结果以确定电路经历的模拟噪声的总输出。然后，使用降低电路模型的计算输出结果来确定原始电路是否被设计成承受减小电路模型所经历的噪声量。

4. 发明申请

US20100262940A1 Accurate Approximation of Resistance in a Wire with Irregular Biasing and Determination of Interconnect Capacitances in VLSI Layouts in the Presence of Catastrophic Optical Proximity Correction 有权
标题翻译：在具有不规则偏移的电线中的电阻的精确近似以及在存在灾难性光学邻近校正的VLSI布局中确定互连电容
公开(公告)号：US20100262940A1
公开(公告)日：2010-10-14
申请号：US12423387
申请日：2009-04-14
申请人： Lewis William Dewey, III , Ibrahim M. Elfadel , David J. Widiger
发明人： Lewis William Dewey, III , Ibrahim M. Elfadel , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： The Width Bias Calculator (WBC) calculates electrical values by effectively averaging the electrical values to either side of a target wire shape whereby values are approximated for design validation without a significant impact on performance or memory consumption.
摘要翻译：宽度偏差计算器（WBC）通过有效地将电气值平均为目标线材形状的任一侧来计算电气值，从而将值近似于设计验证，而不会对性能或存储器消耗产生显着影响。

5. 发明授权

US08645899B2 Method for extracting information for a circuit design 失效
标题翻译：电路设计信息提取方法
公开(公告)号：US08645899B2
公开(公告)日：2014-02-04
申请号：US12415266
申请日：2009-03-31
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

6. 发明申请

US20120204140A1 Generating Capacitance Look-up Tables for Wiring Patterns in the Presence of Metal Fills 失效
标题翻译：在金属填充物的情况下生成接线图形的电容查找表
公开(公告)号：US20120204140A1
公开(公告)日：2012-08-09
申请号：US13449009
申请日：2012-04-17
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

7. 发明授权

US07346867B2 Method for estimating propagation noise based on effective capacitance in an integrated circuit chip 失效
标题翻译：基于集成电路芯片中的有效电容估计传播噪声的方法
公开(公告)号：US07346867B2
公开(公告)日：2008-03-18
申请号：US11048422
申请日：2005-02-01
申请人： Haihua Su , David J. Widiger , Ying Liu , Byron L. Krauter , Chandramouli V. Kashyap
发明人： Haihua Su , David J. Widiger , Ying Liu , Byron L. Krauter , Chandramouli V. Kashyap
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.
摘要翻译：用于估计在驱动器电路的输入处由非零噪声毛刺引起的传播噪声的系统和方法。这种传播噪声是输入噪声毛刺和驱动器输出有效电容性负载两者的函数，这通常是由于深亚微米互连中的电阻屏蔽而导致的总布线电容的一部分。本文提供的噪声驱动的有效电容解决方案还估计在驱动门的输入处由非零噪声毛刺引起的传播噪声。在噪声驱动的有效电容过程中使用描述输出噪声特性和输入噪声特性与输出负载电容之间的关系的门传播噪声规则来确定驱动门的线性戴维宁模型。然后使用线性化的戴维南驱动器模型来分析传播噪声和通常在全局信号网中看到的组合耦合和传播噪声。

8. 发明授权

US08539428B2 Method for extracting information for a circuit design 失效
标题翻译：电路设计信息提取方法
公开(公告)号：US08539428B2
公开(公告)日：2013-09-17
申请号：US13427516
申请日：2012-03-22
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

9. 发明申请

US20120180013A1 METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN 失效
标题翻译：提取电路设计信息的方法
公开(公告)号：US20120180013A1
公开(公告)日：2012-07-12
申请号：US13427486
申请日：2012-03-22
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法包括在与电路设计中的多个电路部件相对应的多个设计形状之间建立反射关系。该方法包括接收多个设计形状的至少一个设计形状的设计变化。该方法包括识别一组改变的形状，一组受影响的形状以及一组涉及的形状。该方法包括基于变化的形状，受影响的形状的集合和所涉及的形状的集合中的至少一个来提取用于更新的电路设计的电容，电感或电阻中的至少一个。所述方法包括基于所述一组改变的形状和所述一组受影响的形状中的至少一个来更新所述电路设计中的所述多个电路部件。

10. 发明申请

US20100251198A1 METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN 失效
标题翻译：提取电路设计信息的方法
公开(公告)号：US20100251198A1
公开(公告)日：2010-09-30
申请号：US12415266
申请日：2009-03-31
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

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