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1. 发明申请

US20120104530A1 SUBSTRATE FOR DISPLAY PANEL, AND DISPLAY DEVICE 审中-公开
标题翻译：显示面板基板和显示设备
公开(公告)号：US20120104530A1
公开(公告)日：2012-05-03
申请号：US13378617
申请日：2010-02-18
申请人： Seiji Kaneko , Masahiro Fujiwara , Hiroshi Aichi , Noboru Takeuchi
发明人： Seiji Kaneko , Masahiro Fujiwara , Hiroshi Aichi , Noboru Takeuchi
IPC分类号： H01L27/146
CPC分类号： G06F3/0412 , G02F1/133514 , G02F1/1362 , G02F2001/13312 , G02F2201/52 , G06F3/042 , H01L27/3227 , H01L27/323
摘要： A display panel substrate includes a plurality of pixels, a pixel in the display panel substrate including a PIN diode for conducting therethrough a different electric current in accordance with an amount of light received by the light receiving element, a first inorganic insulating film formed on the PIN diode, a line formed on or above the first inorganic insulating film and electrically connected to the PIN diode, an organic insulating film formed on or above the line, a transparent pixel electrode formed on the organic insulating film, and a transparent cover electrode provided at such a position that the transparent electrode is located between the organic insulating film and the first inorganic insulating film and formed to cover at least a part of an I-layer of the PIN diode.
摘要翻译：显示面板基板包括多个像素，所述显示面板基板中的像素包括PIN二极管，用于根据由所述光接收元件接收的光量而导致不同的电流;第一无机绝缘膜，形成在所述第二无机绝缘膜上; PIN二极管，形成在第一无机绝缘膜上或上方并与PIN二极管电连接的线，形成在线上或上方的有机绝缘膜，形成在有机绝缘膜上的透明像素电极，以及设置有透明盖电极在透明电极位于有机绝缘膜和第一无机绝缘膜之间并形成以覆盖PIN二极管的I层的至少一部分的位置。

2. 发明申请

US20130088660A1 THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE 审中-公开
标题翻译：薄膜晶体管衬底和液晶显示器件
公开(公告)号：US20130088660A1
公开(公告)日：2013-04-11
申请号：US13703783
申请日：2011-04-26
申请人： Seiji Kaneko
发明人： Seiji Kaneko
IPC分类号： H01L27/15
CPC分类号： H01L27/15 , G02F1/133345 , G02F1/1362 , G02F2001/136218 , H01L27/124 , H01L27/1255
摘要： Disclosed is a liquid crystal display device including a thin film transistor substrate, in which changes in the potential at a pixel electrode can be suppressed without decreasing the aperture ratio of a pixel. Gate wiring lines and source wiring lines are covered with a multilayer insulating film made of two layers of interlayer insulating films that overlap each other. Pixel electrodes are formed on the multilayer insulating film, and a shield electrode, which is formed of a transparent conductive material, is provided between the two layers of interlayer insulating films so as to extend along the gate wiring lines and the source wiring lines and to lie between the gate electrodes or the source electrodes and the pixel electrodes.
摘要翻译：公开了一种液晶显示装置，其包括薄膜晶体管基板，其中可以抑制像素电极处的电位变化而不降低像素的开口率。栅极布线和源极布线被由彼此重叠的两层层间绝缘膜制成的多层绝缘膜覆盖。在多层绝缘膜上形成像素电极，并且在两层层间绝缘膜之间设置由透明导电材料形成的屏蔽电极，以沿着栅极布线和源极布线延伸，并且位于栅电极或源极和像素电极之间。

3. 发明申请

US20120256184A1 SEMICONDUCTOR DEVICE, ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE 有权
标题翻译：半导体器件，有源矩阵衬底和显示器件
公开(公告)号：US20120256184A1
公开(公告)日：2012-10-11
申请号：US13515921
申请日：2010-11-02
申请人： Seiji Kaneko , Hidehito Kitakado
发明人： Seiji Kaneko , Hidehito Kitakado
IPC分类号： H01L29/786
CPC分类号： H01L29/78633 , G02F1/1368 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： A switching element (a semiconductor device) (18) having a top gate electrode (21) and a bottom gate electrode (23) is provided with a silicon layer (a semiconductor layer) (SL) that is arranged between the top gate electrode (21) and the bottom gate electrode (a light-shielding film) (23) and that has a source region (24), a drain region (28), a channel region (26), and low-concentration impurity regions (25, 27). Furthermore, the bottom gate electrode (23) is arranged so as to overlap the channel region (26), a part of the low-concentration impurity region (25), which is adjacent to the source region (24), and a part of the low-concentration impurity region (27), which is adjacent to the drain region (18). The bottom gate electrode (23) is controlled so as to have a prescribed potential.
摘要翻译：具有顶栅极（21）和底栅电极（23）的开关元件（半导体器件）（18）设置有硅层（半导体层）（SL），其设置在顶栅电极 21）和底栅极（遮光膜）（23），并且具有源极区（24），漏极区（28），沟道区（26）和低浓度杂质区（25， 27）。此外，底栅电极（23）被布置成与沟道区（26）重叠，与源区（24）相邻的低浓度杂质区（25）的一部分，和与漏极区（18）相邻的低浓度杂质区（27）。底栅极（23）被控制为具有规定的电位。

4. 发明申请

US20080016285A1 Disk array device, method for controlling the disk array device and storage system 失效
标题翻译：磁盘阵列设备，磁盘阵列设备和存储系统的控制方法
公开(公告)号：US20080016285A1
公开(公告)日：2008-01-17
申请号：US11896657
申请日：2007-09-05
申请人： Seiji Kaneko , Hiroki Kanai
发明人： Seiji Kaneko , Hiroki Kanai
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F3/067 , G06F3/0689 , G06F12/0815 , G06F12/0817 , Y10S707/99952
摘要： A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories connected to each of the corresponding respective input/output channels, a disk drive device, a disk control module that performs data input/output to and from the disk drive device, and a communication module that communicatively connects the input/output channels with the disk control module. The disk array device also includes a consistency maintaining module that can perform a consistency maintaining processing to maintain consistency of data stored in each of the cache memories. According to the content of the data input/output request received from the external device, an execution order of a response processing to respond to the external device according to the data input/output request and the consistency maintaining processing is controlled.
摘要翻译：磁盘阵列装置配备有从外部设备接收数据输入/输出请求的多个输入/输出通道，为相应的相应输入/输出通道提供的多个高速缓存存储器，每个缓存存储器连接到对应的各个输入/输出通道，磁盘驱动器装置，对磁盘驱动装置执行数据输入/输出的磁盘控制模块，以及将输入/输出通道与磁盘控制模块通信连接的通信模块。磁盘阵列设备还包括一致性维护模块，该模块可以执行一致性维持处理以保持存储在每个高速缓冲存储器中的数据的一致性。根据从外部设备接收的数据输入/输出请求的内容，控制根据数据输入/输出请求和一致性维护处理对外部设备进行响应的响应处理的执行顺序。

5. 发明申请

US20070140017A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070140017A1
公开(公告)日：2007-06-21
申请号：US11637026
申请日：2006-12-12
申请人： Seiji Kaneko , Naoki Ueda
发明人： Seiji Kaneko , Naoki Ueda
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2211/5621
摘要： There is provided a nonvolatile semiconductor memory device capable of accelerating writing time and avoiding readout errors of information by eliminating variation in threshold voltage of unselected memory cells. In a nonvolatile semiconductor memory device having a memory cell array with memory cells capable of erasing and programming information, the memory cells store one data value selected from the same number of data values as programming distribution ranges, associated with that the electrical attribute belongs to any one of the more than one programming distribution ranges. The device comprises an erasure means for erasing the selected memory cell to be erased so that its electrical attribute belongs to a erasure distribution range not overlapping any of the programming distribution ranges and a programming means for programming an erased memory cell to be programmed so that its electrical attribute belongs to any one of the programming distribution ranges.
摘要翻译：提供一种非易失性半导体存储器件，其能够通过消除未选择的存储单元的阈值电压的变化来加速写入时间并避免信息的读出错误。在具有具有能够擦除和编程信息的存储器单元的存储单元阵列的非易失性半导体存储器件中，存储器单元存储从与电属性属于任何相关联的编程分配范围相同数量的数据值中选择的一个数据值多个编程分布范围之一。该装置包括擦除装置，用于擦除被擦除的所选择的存储单元，使得其电属性属于不与任何编程分布范围重叠的擦除分布范围，以及编程装置，用于对要编程的擦除存储器单元进行编程，电属性属于编程分布范围中的任何一个。

6. 发明授权

US06519667B2 Bus control system 失效
公开(公告)号：US06519667B2
公开(公告)日：2003-02-11
申请号：US09991925
申请日：2001-11-26
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

7. 发明授权

US06221732B1 Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06221732B1
公开(公告)日：2001-04-24
申请号：US09547903
申请日：2000-04-11
申请人： Seiji Kaneko
发明人： Seiji Kaneko
IPC分类号： H01L2176
CPC分类号： H01L21/7624 , H01L21/76202 , H01L21/84 , H01L27/1203
摘要： A method of producing a semiconductor device comprising the steps of: (a) forming partially an SOI structure portion comprising an insulation layer and a semiconductor layer on a semiconductor substrate; (b) forming selectively a first oxidation-resistant film on a region other than device isolation region-forming portions of the SOI structure portion and of an exposed portion of the semiconductor substrate; (c) forming an oxide film in the device isolation region-forming portions of the semiconductor substrate and of the SOI structure portion under such condition that the semiconductor layer of the SOI structure portion is oxidized up to the bottom of the semiconductor layer; (d) depositing a second oxidation-resistant film over the entire surface of the resultant obtained by the above steps (a) to (c); (e) etching away selectively the second oxidation-resistant film on the exposed portion of the semiconductor substrate using a resist mask so patterned as to cover the SOI structure portion; (f1) implanting an impurity ion into the semiconductor substrate using the resist mask; and (g1) removing the resist mask, and conducting heat-treatment to activate the implanted impurity ion and increase the thickness of the oxide film in the device isolation region-forming portion of the exposed portion of the semiconductor substrate to a predetermined film thickness.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底上部分地形成包括绝缘层和半导体层的SOI结构部分; （b）在SOI结构部分的器件隔离区域形成部分和半导体衬底的暴露部分之外的区域上选择性地形成第一抗氧化膜; （c）在SOI结构部分的半导体层被氧化到半导体层的底部的条件下，在半导体衬底和SOI结构部分的器件隔离区域形成部分中形成氧化物膜; （d）在通过上述步骤（a）至（c）获得的结果的整个表面上沉积第二抗氧化膜; （e）使用如图案化以覆盖SOI结构部分的抗蚀剂掩模来选择性地去除半导体衬底的暴露部分上的第二抗氧化膜; （f1）使用抗蚀剂掩模将杂质离子注入到半导体衬底中; 和（g1）去除抗蚀剂掩模，并进行热处理以激活注入的杂质离子，并将半导体衬底的暴露部分的器件隔离区域形成部分中的氧化物膜的厚度增加到预定的膜厚度。

8. 发明授权

US5841170A Field effect transistor and CMOS element having dopant exponentially graded in channel 失效
标题翻译：场效应晶体管和CMOS元件具有在通道中指数级分的掺杂剂
公开(公告)号：US5841170A
公开(公告)日：1998-11-24
申请号：US782251
申请日：1997-01-14
申请人： Alberto Oscar Adan , Seiji Kaneko
发明人： Alberto Oscar Adan , Seiji Kaneko
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/105
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78612
摘要： A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.
摘要翻译：在SOI衬底上制造场效应晶体管。 N型源极和漏极区域在SOI衬底的半导体薄膜中彼此分开布置。在源区和漏区之间形成P型沟道区。此外，栅极电极形成在沟道区域上，以通过栅极氧化膜覆盖沟道区域。与源区和漏区相邻的沟道区的极端部分的掺杂浓度高于其中心部分。此外，调整沟道区域中的掺杂分布的梯度，以便减小场效应晶体管中寄生晶体管的电流增益。该结构能够将场效应晶体管的沟道长度减小到亚半微米级，而不会使场效应晶体管的电特性恶化。

9. 发明授权

US5774679A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement 失效
公开(公告)号：US5774679A
公开(公告)日：1998-06-30
申请号：US774614
申请日：1996-12-30
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F13/14
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

10. 发明授权

US5426063A Method of making a field effect transistor with submicron channel length and threshold implant using oblique implantation 失效
标题翻译：制造具有亚微米沟道长度的场效应晶体管和使用倾斜植入的阈值植入的方法
公开(公告)号：US5426063A
公开(公告)日：1995-06-20
申请号：US215604
申请日：1994-03-22
申请人： Seiji Kaneko , Tomoya Baba
发明人： Seiji Kaneko , Tomoya Baba
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/7833
摘要： A method for manufacturing a semiconductor device including steps of forming a gate oxide film and a gate electrode on a semiconductor substrate; implanting impurity ions of the same conductivity as the substrate in an oblique direction at a first tilt angle to the normal line of the substrate and with a first acceleration voltage and dose, while rotating the substrate about the normal line thereof; implanting impurities of the same conductivity as the substrate in the same manner except for using a tilt angle to the normal line which is greater and a dose is smaller than that of the first tilt angle and dose; and forming source and drain regions by implanting impurity ions of the opposite conductivity to the substrate into the substrate, followed by performing a thermal treatment.
摘要翻译：一种半导体器件的制造方法，包括在半导体衬底上形成栅极氧化膜和栅电极的步骤; 在基板绕其基准线旋转的同时，以与第一加速电压和第一加速度电压和剂量相对于基板的法线以第一倾斜角倾斜方向注入与基板相同导电性的杂质离子; 以相同的方式注入与衬底相同导电性的杂质，除了使用比法线更大的剂量并且剂量小于第一倾斜角度和剂量的法线的倾斜角; 以及通过将相反导电性的杂质离子注入到衬底中形成源区和漏区，然后进行热处理。

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