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1. 发明申请

US20080063244A1 Biometric apparatus and biometric method 审中-公开
标题翻译：生物测定仪和生物识别方法
公开(公告)号：US20080063244A1
公开(公告)日：2008-03-13
申请号：US11898643
申请日：2007-09-13
申请人： Yuichiro Tanaka , Tetsuya Mochida , Harumi Sato
发明人： Yuichiro Tanaka , Tetsuya Mochida , Harumi Sato
IPC分类号： G06K9/00
CPC分类号： G06K9/00033 , G06K9/00912 , G06K2009/00932
摘要： A biometric apparatus is provided that comprises a personal computer (PC), and a finger vein authentication module connected to the PC, wherein the PC retrieves finger vein position information of an organism from a biometric image obtained during registration of a user for displaying on the screen of a liquid crystal display during authentication, and superimposes current finger contour information obtained during the authentication on the finger contour position information for displaying on the screen of the liquid crystal display. With this, even when the biometric apparatus is not provided with a jig that fixes the organism, it is possible, during the authentication, to cause the organism to match the position and angle a template captured during registration, and to complete the authentication rapidly.
摘要翻译：提供了一种生物测定装置，其包括个人计算机（PC）和连接到PC的手指静脉认证模块，其中PC从用户登记时获得的生物体图像检索生物体的手指静脉位置信息，以便在验证期间的液晶显示器的屏幕，并且将在认证期间获得的当前手指轮廓信息叠加在手指轮廓位置信息上，以在液晶显示器的屏幕上显示。因此，即使生物测定装置没有设置固定生物体的夹具，也可以在认证过程中使生物体与登记时捕获的模板的位置和角度相匹配，并快速完成认证。

2. 发明授权

US07340552B2 Bus control system 失效
标题翻译：总线控制系统
公开(公告)号：US07340552B2
公开(公告)日：2008-03-04
申请号：US11642511
申请日：2006-12-21
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
摘要翻译：在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

3. 发明授权

US06334164B1 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US06334164B1
公开(公告)日：2001-12-25
申请号：US09690998
申请日：2000-10-18
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F1314
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

4. 发明授权

US06195719B1 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US06195719B1
公开(公告)日：2001-02-27
申请号：US09518696
申请日：2000-03-03
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F1314
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and controL buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。该控制系统包括总线存储器连接控制器，分别连接到地址总线和分别由处理器，存储器和系统总线控制的总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

5. 发明授权

US6006302A Multiple bus system using a data transfer unit 失效
标题翻译：多总线系统使用数据传输单元
公开(公告)号：US6006302A
公开(公告)日：1999-12-21
申请号：US276968
申请日：1999-03-26
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/40 , G06F13/14
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

6. 发明授权

US5881255A Bus control system incorporating the coupling of two split-transaction busses of different hierarchy 失效
公开(公告)号：US5881255A
公开(公告)日：1999-03-09
申请号：US847974
申请日：1997-04-21
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/36 , G06F3/00 , G06F5/00 , G06F13/00 , G06F13/368 , G06F13/40 , G06F12/00
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

7. 发明授权

US5671371A Bus control system 失效
标题翻译：总线控制系统
公开(公告)号：US5671371A
公开(公告)日：1997-09-23
申请号：US544727
申请日：1995-10-18
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/36 , G06F3/00 , G06F5/00 , G06F13/00 , G06F13/368 , G06F13/40 , G06I13/00
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
摘要翻译：在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

8. 发明授权

US5506973A Bus system for use with information processing apparatus 失效
公开(公告)号：US5506973A
公开(公告)日：1996-04-09
申请号：US443361
申请日：1995-05-17
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/14
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

9. 发明授权

US4990907A Method and apparatus for data transfer 失效
标题翻译：用于数据传输的方法和装置
公开(公告)号：US4990907A
公开(公告)日：1991-02-05
申请号：US231000
申请日：1988-08-11
申请人： Masami Jikihara , Shigeo Tsujioka , Hiromichi Enomoto , Tetsuya Mochida , Masataka Kobayashi
发明人： Masami Jikihara , Shigeo Tsujioka , Hiromichi Enomoto , Tetsuya Mochida , Masataka Kobayashi
IPC分类号： G06F13/42
CPC分类号： G06F13/4213
摘要： A bus master and a plurality of bus slaves are connected through a data bus and a control bus, and data transfer of hand shake system is performed. In the control bus, at least data strobe signal from the bus master to the bus slave and data confirmation signal from the bus slave to the bus master are transmitted. The data strobe signal from the bus master is one inputted to a bus strobe control circuit. The data confirmation signal from the bus slave is also inputted to the bus strobe control circuit, and the control circuit supervises level of the data confirmation signal being asserted and confirms negation, and then asserts the data strobe signal to the bus slave. Thereafter, a next data transfer is started.
摘要翻译：通过数据总线和控制总线连接总线主机和多个总线从机，执行手抖动系统的数据传送。在控制总线中，至少从总线主机到总线从站的数据选通信号和从总线从站到总线主站的数据确认信号。来自总线主机的数据选通信号是输入到总线选通控制电路的信号。来自总线从站的数据确认信号也被输入到总线选通控制电路，控制电路对数据确认信号的电平进行监控，并确认为否定，然后将数据选通信号置为总线从站。此后，开始下一次数据传送。

10. 发明申请

US20090276557A1 BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS 失效
标题翻译：使用信息处理设备的总线系统
公开(公告)号：US20090276557A1
公开(公告)日：2009-11-05
申请号：US12501684
申请日：2009-07-13
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/28
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以经由其间的数据总线传送数据，取决于t

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